PIC18F26K80T-I/SS Microchip Technology, PIC18F26K80T-I/SS Datasheet - Page 269
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PIC18F26K80T-I/SS
Manufacturer Part Number
PIC18F26K80T-I/SS
Description
ECAN, 64KB Flash, 4KB RAM, 16 MIPS, 12-bit ADC, CTMU 28 SSOP .209in T/R
Manufacturer
Microchip Technology
Series
PIC® XLP™ 18Fr
Datasheet
1.PIC18F25K80-ISO.pdf
(628 pages)
Specifications of PIC18F26K80T-I/SS
Core Processor
PIC
Core Size
8-Bit
Speed
64MHz
Connectivity
ECAN, I²C, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
24
Program Memory Size
64KB (32K x 16)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
3.6K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Processor Series
PIC18F26K80
Core
PIC
Data Bus Width
8 bit
Data Ram Size
1 KB
Interface Type
I2C, SPI, USART
Maximum Clock Frequency
64 MHz
Number Of Programmable I/os
24
Number Of Timers
5
Operating Supply Voltage
1.8 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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19.4.2
The PWM duty cycle is specified, to use CCP4 as an
example, by writing to the CCPR4L register and to the
CCP4CON<5:4> bits. Up to 10-bit resolution is avail-
able. The CCPR4L contains the eight MSbs and the
CCP4CON<5:4> contains the two LSbs. This 10-bit
value is represented by CCPR4L:CCP4CON<5:4>.
The following equation is used to calculate the PWM
duty cycle in time:
EQUATION 19-2:
CCPR4L and CCP4CON<5:4> can be written to at any
time, but the duty cycle value is not latched into
CCPR4H until after a match between PR2 and TMR2
occurs (that is, the period is complete). In PWM mode,
CCPR4H is a read-only register.
TABLE 19-4:
19.4.3
To configure the CCP module for PWM operation,
using CCP4 as an example:
1.
2.
2011 Microchip Technology Inc.
Timer Prescaler (1, 4, 16)
PR2 Value
Maximum Resolution (bits)
PWM Duty Cycle = (CCPR4L:CCP4CON<5:4>) •
Set the PWM period by writing to the PR2
register.
Set the PWM duty cycle by writing to the
CCPR4L register and CCP4CON<5:4> bits.
PWM Frequency
PWM DUTY CYCLE
SETUP FOR PWM OPERATION
EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 40 MHz
T
OSC
• (TMR2 Prescale Value)
2.44 kHz
FFh
16
10
9.77 kHz
Preliminary
FFh
10
4
PIC18F66K80 FAMILY
39.06 kHz
The CCPR4H register and a two-bit internal latch are
used to double-buffer the PWM duty cycle. This
double-buffering is essential for glitchless PWM
operation.
When the CCPR4H and two-bit latch match TMR2,
concatenated with an internal two-bit Q clock or two
bits of the TMR2 prescaler, the CCP4 pin is cleared.
The maximum PWM resolution (bits) for a given PWM
frequency is given by the equation:
EQUATION 19-3:
3.
4.
5.
Note:
FFh
10
1
Make the CCP4 pin an output by clearing the
appropriate TRIS bit.
Set the TMR2 prescale value, then enable
Timer2 by writing to T2CON.
Configure the CCP4 module for PWM operation.
PWM Resolution (max)
If the PWM duty cycle value is longer than
the PWM period, the CCP4 pin will not be
cleared.
156.25 kHz
3Fh
1
8
312.50 kHz
=
1Fh
1
7
log
-----------------------------bits
log
DS39977C-page 269
---------------
F
F
PWM
2
OSC
416.67 kHz
6.58
17h
1
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