PIC18F26K80-I/MM Microchip Technology, PIC18F26K80-I/MM Datasheet - Page 280
![ECAN, 64KB Flash, 4KB RAM, 16 MIPS, 12-bit ADC, CTMU 28 QFN-S 6x6mm TUBE](/photos/16/12/161267/qfn-28_sml.jpg)
PIC18F26K80-I/MM
Manufacturer Part Number
PIC18F26K80-I/MM
Description
ECAN, 64KB Flash, 4KB RAM, 16 MIPS, 12-bit ADC, CTMU 28 QFN-S 6x6mm TUBE
Manufacturer
Microchip Technology
Series
PIC® XLP™ 18Fr
Datasheet
1.PIC18F25K80-ISO.pdf
(628 pages)
Specifications of PIC18F26K80-I/MM
Core Processor
PIC
Core Size
8-Bit
Speed
64MHz
Connectivity
ECAN, I²C, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
24
Program Memory Size
64KB (32K x 16)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
3.6K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-VQFN Exposed Pad
Processor Series
PIC18F26K80
Core
PIC
Data Bus Width
8 bit
Data Ram Size
3648 B
Interface Type
I2C, SPI
Maximum Clock Frequency
64 MHz
Number Of Programmable I/os
24
Number Of Timers
5
Operating Supply Voltage
1.8 V to 5.5 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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PIC18F66K80 FAMILY
20.4.1
In Half-Bridge mode, two pins are used as outputs to
drive push-pull loads. The PWM output signal is output
on the P1A pin, while the complementary PWM output
signal is output on the P1B pin (see
mode can be used for half-bridge applications, as
shown in
where four power switches are being modulated with
two PWM signals.
In Half-Bridge mode, the programmable dead-band delay
can be used to prevent shoot-through current in
half-bridge power devices. The value of the P1DC<6:0>
bits of the ECCP1DEL register sets the number of
instruction cycles before the output is driven active. If the
value is greater than the duty cycle, the corresponding
output remains inactive during the entire cycle. For more
details on the dead-band delay operations, see
Section 20.4.6 “Programmable Dead-Band Delay
Mode”
FIGURE 20-7:
DS39977C-page 280
.
Standard Half-Bridge Circuit (“Push-Pull”)
Half-Bridge Output Driving a Full-Bridge Circuit
Figure
HALF-BRIDGE MODE
20-7, or for full-bridge applications,
EXAMPLE OF HALF-BRIDGE APPLICATIONS
P1A
P1B
Figure
P1A
P1B
20-6). This
FET
Driver
FET
Driver
Preliminary
FET
Driver
FET
Driver
Since the P1A and P1B outputs are multiplexed with
the port data latches, the associated TRIS bits must be
cleared to configure P1A and P1B as outputs.
FIGURE 20-6:
P1A
P1B
td = Dead-Band Delay
Note 1: At this time, the TMR2 register is equal to the
Load
(2)
(2)
V+
2: Output signals are shown as active-high.
(1)
td
PR2 register.
Pulse Width
Load
Period
td
EXAMPLE OF
HALF-BRIDGE PWM
OUTPUT
2011 Microchip Technology Inc.
FET
Driver
FET
Driver
+
-
+
-
(1)
Period
(1)
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