PIC18F26K80-E/SS Microchip Technology, PIC18F26K80-E/SS Datasheet - Page 268

• Manufacturer Part Number: PIC18F26K80-E/SS
• Description: ECAN, 64KB Flash, 4KB RAM, 16 MIPS, 12-bit ADC, CTMU 28 SSOP .209in TUBE
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18F26K80-E/SS

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 64MHz
• Connectivity: ECAN, I²C, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Size: 64KB (32K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 3.6K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: *
• Processor Series: PIC18F26K80
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: I2C, SPI, USART
• Maximum Clock Frequency: 64 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 5
• Operating Supply Voltage: 1.8 V to 5.5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PIC18F66K80 FAMILY
19.4
In Pulse-Width Modulation (PWM) mode, the CCPx pin
produces up to a 10-bit resolution PWM output. Since
the CCPx pin is multiplexed with a PORTC or PORTB
data latch, the appropriate TRIS bit must be cleared to
make the CCPx pin an output.
Figure 19-3
CCPx module in PWM mode.
For a step-by-step procedure on how to set up the CCP
module for PWM operation, see
“Setup for PWM Operation”
FIGURE 19-3:
DS39977C-page 268
Note:
Note 1:
CCPR4H (Slave)
Duty Cycle Registers
Comparator
CCPR4L
TMR2
2:
PR2
Comparator
PWM Mode
The 8-bit TMR2 value is concatenated with the 2-bit
internal Q clock, or 2 bits of the prescaler, to create
the 10-bit time base.
CCP4 and its appropriate timers are used as an
example. For details on all of the CCP modules and
their timer assignments, see
Clearing the CCPxCON register will force
the corresponding CCPx output latch
(depending on device configuration) to the
default low level. This is not the PORTx
I/O data latch.
shows a simplified block diagram of the
(Note 1)
Clear Timer,
CCP1 Pin and
Latch D.C.
SIMPLIFIED PWM BLOCK
DIAGRAM
CCP4CON<5:4>
.
R
S
Table
Q
19-2.
TRISC<2>
Section 19.4.3
RC2/CCP1
Preliminary
A PWM output
and a time that the output stays high (duty cycle). The
frequency of the PWM is the inverse of the period
(1/period).
FIGURE 19-4:
19.4.1
The PWM period is specified by writing to the PR2
register. The PWM period can be calculated using the
following formula:
EQUATION 19-1:
PWM frequency is defined as 1/[PWM period].
When TMR2 is equal to PR2, the following three events
occur on the next increment cycle:
• TMR2 is cleared
• The CCP4 pin is set
• The PWM duty cycle is latched from CCPR4L into
(An exception: If PWM duty cycle = 0%, the CCP4
pin will not be set)
CCPR4H
Note:
PWM Period = [(PR2) + 1] • 4 • T
TMR2 = PR2
Duty Cycle
PWM PERIOD
The
Section 15.0 “Timer2 Module”
used in the determination of the PWM
frequency. The postscaler could be used
to have a servo update rate at a different
frequency than the PWM output.
(Figure
Period
TMR2 = Duty Cycle
Timer2
(TMR2 Prescale Value)
PWM OUTPUT
19-4) has a time base (period)
 2011 Microchip Technology Inc.
TMR2 = PR2
postscalers
OSC
•
) are not
(see