PIC18F23K20-E/SP Microchip Technology, PIC18F23K20-E/SP Datasheet - Page 3

• Manufacturer Part Number: PIC18F23K20-E/SP
• Description: 8 KB Enh Flash, 768 RAM, 25 I/O Pb Free, Nanowatt XLP 28 SPDIP .300in TUBE
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18F23K20-E/SP

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 48MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Size: 8KB (4K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 11x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 28-DIP (0.300", 7.62mm)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Silicon Errata Issues
1. Module: ECCP
2. Module: ECCP
 2010 Microchip Technology Inc.
Note:
Changing direction in Full-Bridge mode inserts a
dead band time of 4/F
instead of 1/F
in the data sheet.
Work around
None.
Affected Silicon Revisions
PIC18F23/43K20
In Full-Bridge mode when PR2 = CCPR1L and
DC1B<1:0> = 00 and the direction is changed
then the dead time before the modulated output
starts is compromised. The modulated signal
improperly starts immediately with the direction
change
Tosc * TMR2Presale * DC1B<1:0>.
Work around
Avoid changing direction when the duty cycle is
within three Least Significant steps of 100% duty
cycle. Instead, clear the DC1B<1:0> bits before
the direction change and then set them to the
desired value after the direction change is
complete.
Affected Silicon Revisions
PIC18F23/43K20
A0
A0
X
X
This document summarizes all silicon
errata issues from all revisions of silicon,
previous as well as current. Only the
issues indicated by the shaded column in
the following tables apply to the current
silicon revision (A0 or A2, as applicable).
A1
A1
X
X
OSC
and
* (TMR2 Prescale) as specified
stays
OSC
* (TMR2 Prescale)
on
for
3. Module: MSSP (SPI clock)
4. Module: MSSP (SPI Master mode)
When the SPI clock is configured for Timer2/2
(SSPCON1<3:0> = 0011), and the CKE bit of the
SSPSTAT register is ‘1’, then when SSPBUF is
written the SCK output is improperly and immedi-
ately driven to the non-Idle state together with the
MSb value of the SSPBUF. The duration at which
SDO and SCK remain at these levels may be
shorter than a full half-bit period. The remaining
bits in the byte are output properly.
Work around
None.
Affected Silicon Revisions
PIC18F23/43K20
In SPI Master mode, when the CKE bit of the
SSPSTAT register is cleared and the SMP bit of
the SSPSTAT register is set, then the last bit of the
incoming data stream (bit 0) at the SDI pin will not
be sampled properly.
Work around
none.
Affected Silicon Revisions
PIC18F23/43K20
A0
A0
X
X
PIC18F23/43K20
A1
A1
X
X
DS80469C-page 3