PIC18F23K20-E/MV Microchip Technology, PIC18F23K20-E/MV Datasheet - Page 224
![8 KB Enh Flash, 768 RAM, 25 I/O Pb Free, Nanowatt XLP 28 UQFN 4x4x0.5mm TUBE](/photos/12/13/121305/c04-152_mv_sml.jpg)
PIC18F23K20-E/MV
Manufacturer Part Number
PIC18F23K20-E/MV
Description
8 KB Enh Flash, 768 RAM, 25 I/O Pb Free, Nanowatt XLP 28 UQFN 4x4x0.5mm TUBE
Manufacturer
Microchip Technology
Series
PIC® XLP™ 18Fr
Specifications of PIC18F23K20-E/MV
Core Processor
PIC
Core Size
8-Bit
Speed
48MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, HLVD, POR, PWM, WDT
Number Of I /o
24
Program Memory Size
8KB (4K x 16)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Data Converters
A/D 11x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
28-UFQFN Exposed Pad
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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PIC18F2XK20/4XK20
17.4.9
A Repeated Start condition occurs when the RSEN bit
of the SSPCON2 register is programmed high and the
I
is set, the SCL pin is asserted low. When the SCL pin
is sampled low, the Baud Rate Generator is loaded with
the contents of SSPADD<5:0> and begins counting.
The SDA pin is released (brought high) for one Baud
Rate Generator count (T
Generator times out, if SDA is sampled high, the SCL
pin will be deasserted (brought high). When SCL is
sampled high, the Baud Rate Generator is reloaded
with the contents of SSPADD<7:0> and begins count-
ing. SDA and SCL must be sampled high for one T
This action is then followed by assertion of the SDA pin
(SDA = 0) for one T
this, the RSEN bit of the SSPCON2 register will be
automatically cleared and the Baud Rate Generator will
not be reloaded, leaving the SDA pin held low. As soon
as a Start condition is detected on the SDA and SCL
pins, the S bit of the SSPSTAT register will be set. The
SSPIF bit will not be set until the Baud Rate Generator
has timed out.
FIGURE 17-20:
DS41303G-page 224
2
C logic module is in the Idle state. When the RSEN bit
I
START CONDITION TIMING
2
C MASTER MODE REPEATED
on falling edge of ninth clock,
RSEN bit set by hardware
BRG
REPEAT START CONDITION WAVEFORM
SDA
SCL
while SCL is high. Following
BRG
). When the Baud Rate
end of Xmit
Write to SSPCON2
occurs here.
SDA = 1,
SCL (no change).
BRG
T
SDA = 1,
SCL = 1
.
BRG
T
BRG
Immediately following the SSPIF bit getting set, the user
may write the SSPBUF with the 7-bit address in 7-bit
mode or the default first address in 10-bit mode. After the
first eight bits are transmitted and an ACK is received,
the user may then transmit an additional eight bits of
address (10-bit mode) or eight bits of data (7-bit mode).
17.4.9.1
If the user writes the SSPBUF when a Repeated Start
sequence is in progress, the WCOL is set and the
contents of the buffer are unchanged (the write doesn’t
occur).
Note:
Note 1: If RSEN is programmed while any other
Sr = Repeated Start
T
BRG
2: A bus collision during the Repeated Start
At completion of Start bit,
hardware clears RSEN bit
S bit set by hardware
and sets SSPIF
Because queueing of events is not
allowed, writing of the lower 5 bits of
SSPCON2 is disabled until the Repeated
Start condition is complete.
Write to SSPBUF occurs here
event is in progress, it will not take effect.
condition occurs if:
• SDA is sampled low when SCL goes
• SCL goes low before SDA is
WCOL Status Flag
T
from low-to-high.
asserted low. This may indicate that
another master is attempting to
transmit a data ‘1’.
BRG
1st bit
T
BRG
2010 Microchip Technology Inc.
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