PIC18F2221-E/ML Microchip Technology, PIC18F2221-E/ML Datasheet - Page 5

• Manufacturer Part Number: PIC18F2221-E/ML
• Description: 4KB, Flash, 512bytes-RAM, 25I/O, 8-bit Family,nanoWatt 28 QFN 6x6mm TUBE
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F2221-E/ML

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 25
• Program Memory Size: 4KB (2K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

2. Module: CONFIG4L Register
REGISTER 23-5:
 2010 Microchip Technology Inc.
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7
bit 6
bit 5-4
bit 3
bit 2
bit 1
bit 0
DEBUG
Register 23-5 CONFIG4L: Configuration Regis-
ter 4 Low (Byte Address 300006h), on Page 258,
has been changed to designate Bit 3 of
CONFIG4L as unimplemented.
The register is changed as shown.
R/P-1
DEBUG: Background Debugger Enable bit
1 = Background debugger disabled, RB6 and RB7 configured as general purpose I/O pins
0 = Background debugger enabled, RB6 and RB7 are dedicated to In-Circuit Debug
XINST: Extended Instruction Set Enable bit
1 = Instruction set extension and Indexed Addressing mode enabled
0 = Instruction set extension and Indexed Addressing mode disabled (Legacy mode)
BBSIZ<1:0>: Boot Block Size Select bits
Feature2 Devices:
1x = 1024 Words
01 = 512 Words
00 = 256 Words
Feature1 Devices:
1x = 512 Words
x1 = 512 Words
00 = 256 Words
Unimplemented: Read as ‘0’
LVP: Single-Supply ICSP™ Enable bit
1 = Single-Supply ICSP enabled
0 = Single-Supply ICSP disabled
Unimplemented: Read as ‘0’
STVREN: Stack Full/Underflow Reset Enable bit
1 = Stack full/underflow will cause Reset
0 = Stack full/underflow will not cause Reset
XINST
R/P-0
CONFIG4L: CONFIGURATION REGISTER 4 LOW (BYTE ADDRESS 300006h)
W = Writable bit
‘1’ = Bit is set
BBSIZ1
U-0
PIC18F2221/2321/4221/4321
BBSIZ0
U-0
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
U-0
—
R/P-1
LVP
x = Bit is unknown
U-0
—
DS80285C-page 5
STVREN
R/P-1
bit 0