PIC18F13K50T-I/SO Microchip Technology, PIC18F13K50T-I/SO Datasheet - Page 19

• Manufacturer Part Number: PIC18F13K50T-I/SO
• Description: 8 KB Flash, 512 RAM, 15 I/O, 10-bit ADC, USB 2.0 20 SOIC .300in T/R
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18F13K50T-I/SO

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 48MHz
• Connectivity: I²C, SPI, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 14
• Program Memory Size: 8KB (4K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 11x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 20-SOIC (7.5mm Width)
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Interface Type: EUSART, I2C, MSSP, SPI, USB
• Maximum Clock Frequency: 48 MHz
• Number Of Programmable I/os: 15
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, DM164127, DV164126
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 11 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: DV164126 - KIT DEVELOPMENT USB W/PICKIT 2DM164127 - KIT DEVELOPMENT USB 18F14/13K50AC164112 - VOLTAGE LIMITER MPLAB ICD2 VPPXLT20SO1-1 - SOCKET TRANS ICE 20DIP TO 20SOIC
• Lead Free Status / Rohs Status: Details

4.3
Data EEPROM is accessed one byte at a time via an
Address Pointer (register pair EEADRH:EEADR) and a
data latch (EEDATA). Data EEPROM is written by
loading EEADRH:EEADR with the desired memory
location, EEDATA, with the data to be written and initi-
ating a memory write by appropriately configuring the
EECON1 register. A byte write automatically erases the
location and writes the new data (erase-before-write).
When using the EECON1 register to perform a data
EEPROM write, both the EEPGD and CFGS bits must
be cleared (EECON1<7:6> = 00). The WREN bit must
be set (EECON1<2> = 1) to enable writes of any sort
and this must be done prior to initiating a write
sequence. The write sequence is initiated by setting the
WR bit (EECON1<1> = 1).
The write begins on the falling edge of the 24th PGC
after the WR bit is set. It ends when the WR bit is
cleared by hardware.
After the programming sequence terminates, PGC
must be held low for the time specified by parameter
P10 to allow high-voltage discharge of the memory
array.
FIGURE 4-7:
 2010 Microchip Technology Inc.
PGC
PGD
Poll WR bit
Data EEPROM Programming
4-bit Command
1
0
2
0
3
0
4
PGD
0
PGC
P5
DATA EEPROM WRITE TIMING DIAGRAM
BSF EECON1, WR
1
4-bit Command
2
1
0
2
0
15 16
3
0
4
0
P5A
P5
MOVF EECON1, W, 0
PIC18F1XK50/PIC18LF1XK50
2 NOP commands
1
Advance Information
2
PGD = Input
PGD = Input
15 16
P5A
P5A
4-bit Command
1
0
FIGURE 4-6:
2
0
3
0
4
0
Poll WR bit, Repeat until Clear
P5
MOVWF TABLAT
1
(see below)
No
2
P11A
15 16
PROGRAM DATA FLOW
Enable Write
Set Address
Start Write
Sequence
Set Data
WR bit
clear?
done?
Start
Done
P5A
Yes
Yes
(see Figure 4-4)
PGD = Output
Shift Out Data
DS41342E-page 19
No
P10
16-bit Data
Payload
1
n
2
n