PIC18F13K22-E/SO Microchip Technology, PIC18F13K22-E/SO Datasheet - Page 139
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PIC18F13K22-E/SO
Manufacturer Part Number
PIC18F13K22-E/SO
Description
8KB Flash, 256bytes RAM, 256bytes EEPROM, 16MIPS, 1.8-5.5V Operation 20 SOIC .30
Manufacturer
Microchip Technology
Series
PIC® XLP™ 18Fr
Specifications of PIC18F13K22-E/SO
Core Processor
PIC
Core Size
8-Bit
Speed
48MHz
Connectivity
I²C, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
17
Program Memory Size
8KB (4K x 16)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
20-SOIC (7.5mm Width)
Processor Series
PIC18F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
256 B
Interface Type
EUSART, I2C, SPI
Maximum Clock Frequency
64 MHz
Number Of Programmable I/os
18
Number Of Timers
4
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 12 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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14.2.3
To enable the serial port, SSP Enable bit, SSPEN of
the SSPCON1 register, must be set. To reset or recon-
figure SPI mode, clear the SSPEN bit, reinitialize the
SSPCON registers and then set the SSPEN bit. This
configures the SDI, SDO, SCK and SS pins as serial
port pins. For the pins to behave as the serial port func-
tion, some must have their data direction bits (in the
TRIS register) appropriately programmed as follows:
• SDI is automatically controlled by the SPI module
• SDO must have corresponding TRIS bit cleared
• SCK (Master mode) must have corresponding
• SCK (Slave mode) must have corresponding
• SS must have corresponding TRIS bit set
Any serial port function that is not desired may be
overridden by programming the corresponding data
direction (TRIS) register to the opposite value.
FIGURE 14-2:
2010 Microchip Technology Inc.
TRIS bit cleared
TRIS bit set
SPI Master SSPM<3:0> = 00xx
ENABLING SPI I/O
MSb
Serial Input Buffer
Processor 1
Shift Register
TYPICAL SPI MASTER/SLAVE CONNECTION
(SSPBUF)
(SSPSR)
LSb
General I/O
SCK
SDO
SDI
Preliminary
Serial Clock
Slave Select
(optional)
PIC18F1XK22/LF1XK22
14.2.4
Figure 14-2 shows a typical connection between two
microcontrollers. The master controller (Processor 1)
initiates the data transfer by sending the SCK signal.
Data is shifted out of both shift registers on their pro-
grammed clock edge and latched on the opposite edge
of the clock. Both processors should be programmed to
the same Clock Polarity (CKP), then both controllers
would send and receive data at the same time.
Whether the data is meaningful (or dummy data)
depends on the application software. This leads to
three scenarios for data transmission:
• Master sends data–Slave sends dummy data
• Master sends data–Slave sends data
• Master sends dummy data–Slave sends data
SDO
SCK
SDI
SS
TYPICAL CONNECTION
SPI Slave SSPM<3:0> = 010x
MSb
Serial Input Buffer
Shift Register
(SSPBUF)
(SSPSR)
Processor 2
LSb
DS41365D-page 139
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