PIC16LF727T-I/MV Microchip Technology, PIC16LF727T-I/MV Datasheet - Page 173
PIC16LF727T-I/MV
Manufacturer Part Number
PIC16LF727T-I/MV
Description
14 KB Flash, 16 MHz Int. Osc, NanoWatt XLP 40 UQFN 5x5x0.5mm T/R
Manufacturer
Microchip Technology
Series
PIC® XLP™ 16Fr
Datasheet
1.AC164112.pdf
(302 pages)
Specifications of PIC16LF727T-I/MV
Processor Series
PIC16F
Core
PIC
Program Memory Type
Flash
Program Memory Size
7 KB
Data Ram Size
192 B
Interface Type
I2C, SPI, AUSART
Number Of Timers
3
Operating Supply Voltage
1.8 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Package / Case
UQFN-44
Development Tools By Supplier
MPLAB IDE Software
Minimum Operating Temperature
- 40 C
Core Processor
PIC
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
36
Eeprom Size
-
Ram Size
368 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Data Converters
A/D 14x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Lead Free Status / Rohs Status
Details
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17.1.2.4
The SS pin allows Synchronous Slave mode operation.
The SPI must be in Slave mode with SS pin control
enabled (SSPM<3:0> = 0100). The associated TRIS bit
for the SS pin must be set, making SS an input.
In Slave Select mode, when:
• SS = 0, The device operates as specified in
• SS = 1, The SPI module is held in Reset and the
FIGURE 17-6:
© 2009 Microchip Technology Inc.
SS
SCK
(CKP = 0
CKE = 0)
SCK
(CKP = 1
CKE = 0)
Write to
SSPBUF
SDO
SDI
(SMP = 0)
Input
Sample
(SMP = 0)
SSPIF
Interrupt
Flag
SSPSR to
SSPBUF
Section 17.1.2 “Slave Mode”.
SDO pin will be tri-stated.
Note 1: When the SPI is in Slave mode with SS pin
2: If the SPI is used in Slave mode with CKE
control enabled (SSPM<3:0> = 0100), the
SPI module will reset if the SS pin is driven
high.
set, the SS pin control must be enabled.
Slave Select Operation
SLAVE SELECT SYNCHRONIZATION WAVEFORM
bit 7
bit 7
bit 6
PIC16F72X/PIC16LF72X
When the SPI module resets, the bit counter is cleared
to ‘0’. This can be done by either forcing the SS pin to
a high level or clearing the SSPEN bit. Figure 17-6
shows the timing waveform for such a synchronization
event.
17.1.2.5
While in Sleep mode, the slave can transmit/receive
data. The SPI Transmit/Receive Shift register operates
asynchronously to the device on the externally supplied
clock source. This allows the device to be placed in
Sleep mode and data to be shifted into the SPI Trans-
mit/Receive Shift register. When all 8 bits have been
received, the SSP Interrupt Flag bit will be set and if
enabled, will wake the device from Sleep.
Note:
SSPSR must be reinitialized by writing to
the SSPBUF register before the data can
be clocked out of the slave again.
SSPSR must be reinitialized by writing to
the SSPBUF register before the data can
be clocked out of the slave again.
Sleep in Slave Mode
bit 7
bit 7
DS41341E-page 173
bit 0
bit 0
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