PIC16LF723A-I/MV Microchip Technology, PIC16LF723A-I/MV Datasheet - Page 133
![no-image](/images/manufacturer_photos/0/4/439/microchip_technology_sml.jpg)
PIC16LF723A-I/MV
Manufacturer Part Number
PIC16LF723A-I/MV
Description
7 KB Flash, 16 MHz Int. Osc, NanoWatt XLP 28 UQFN 4x4x0.5mm TUBE
Manufacturer
Microchip Technology
Series
PIC® XLP™ 16Fr
Datasheet
1.PIC16F722AT-ISS.pdf
(284 pages)
Specifications of PIC16LF723A-I/MV
Core Processor
PIC
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
25
Program Memory Size
7KB (4K x 14)
Program Memory Type
FLASH
Ram Size
192 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Data Converters
A/D 11x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-UFQFN Exposed Pad
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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16.0
The
Asynchronous
module is a serial I/O communications peripheral. It
contains all the clock generators, shift registers and
data buffers necessary to perform an input or output
serial data transfer independent of device program
execution. The AUSART, also known as a Serial
Communications Interface (SCI), can be configured as
a full-duplex asynchronous system or half-duplex
synchronous system. Full-Duplex mode is useful for
communications with peripheral systems, such as CRT
terminals
Synchronous mode is intended for communications
with peripheral devices, such as A/D or D/A integrated
circuits, serial EEPROMs or other microcontrollers.
These devices typically do not have internal clocks for
baud rate generation and require the external clock
signal provided by a master synchronous device.
FIGURE 16-1:
2010 Microchip Technology Inc.
Baud Rate Generator
Addressable
ADDRESSABLE UNIVERSAL
SYNCHRONOUS
ASYNCHRONOUS RECEIVER
TRANSMITTER (AUSART)
and
SPBRG
Receiver
personal
+ 1
AUSART TRANSMIT BLOCK DIAGRAM
F
Multiplier
OSC
Universal
SYNC
BRGH
computers.
Transmitter
TXEN
÷ n
x4
1
x
n
x16 x64
0
1
Synchronous
Half-Duplex
(AUSART)
0
0
MSb
(8)
Transmit Shift Register (TSR)
TX9D
TXREG Register
• • •
TX9
PIC16F/LF722A/723A
The AUSART module includes the following capabilities:
• Full-duplex asynchronous transmit and receive
• Two-character input buffer
• One-character output buffer
• Programmable 8-bit or 9-bit character length
• Address detection in 9-bit mode
• Input buffer overrun error detection
• Received character framing error detection
• Half-duplex synchronous master
• Half-duplex synchronous slave
• Sleep operation
Block diagrams of the AUSART transmitter and
receiver are shown in Figure 16-1 and Figure 16-2.
8
Data Bus
TRMT
LSb
0
TXIF
TXIE
Pin Buffer
and Control
SPEN
DS41417A-page 133
Interrupt
TX/CK
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