PIC16LF1907-E/PT Microchip Technology, PIC16LF1907-E/PT Datasheet - Page 162
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PIC16LF1907-E/PT
Manufacturer Part Number
PIC16LF1907-E/PT
Description
14KB Flash, 512B RAM, LCD, 14x10b ADC, EUSART, NanoWatt XLP 44 TQFP 10x10x1mm TR
Manufacturer
Microchip Technology
Series
PIC® XLP™ 16Fr
Datasheet
1.PIC16LF1904-EMV.pdf
(288 pages)
Specifications of PIC16LF1907-E/PT
Core Processor
PIC
Core Size
8-Bit
Speed
20MHz
Connectivity
LIN, UART/USART
Peripherals
Brown-out Detect/Reset, LCD, POR, PWM, WDT
Number Of I /o
36
Program Memory Size
14KB (8K x 14)
Program Memory Type
FLASH
Eeprom Size
-
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Data Converters
A/D 14x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
44-TQFP
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC16LF1907-E/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
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PIC16LF1904/6/7
18.1.2.9
1.
2.
3.
4.
5.
6.
7.
8.
9.
10. Get the received 8 Least Significant data bits
11. If an overrun occurred, clear the OERR flag by
DS41569A-page 162
Initialize the SPBRGH:SPBRGL register pair
and the BRGH and BRG16 bits to achieve the
desired baud rate (see
Baud Rate Generator
Set the RX/DT and TX/CK TRIS controls to ‘1’.
Enable the serial port by setting the SPEN bit
and the RX/DT pin TRIS bit. The SYNC bit must
be clear for asynchronous operation.
If interrupts are desired, set the RCIE interrupt
enable bit and set the GIE and PEIE bits of the
INTCON register.
If 9-bit reception is desired, set the RX9 bit.
Set the DTRXP if inverted receive polarity is
desired.
Enable reception by setting the CREN bit.
The RCIF interrupt flag bit will be set when a
character is transferred from the RSR to the
receive buffer. An interrupt will be generated if
the RCIE interrupt enable bit was also set.
Read the RCSTA register to get the error flags
and, if 9-bit data reception is enabled, the ninth
data bit.
from the receive buffer by reading the RCREG
register.
clearing the CREN receiver enable bit.
Asynchronous Reception Set-up:
Section 18.3 “EUSART
(BRG)”).
Preliminary
18.1.2.10
This mode would typically be used in RS-485 systems.
To set up an asynchronous reception with address
detect enable:
1.
2.
3.
4.
5.
6.
7.
8.
9.
10. Read the RCSTA register to get the error flags.
11. Get the received 8 Least Significant data bits
12. If an overrun occurred, clear the OERR flag by
13. If the device has been addressed, clear the
Initialize the SPBRGH, SPBRGL register pair
and the BRGH and BRG16 bits to achieve the
desired baud rate (see
Baud Rate Generator
Set the RX/DT and TX/CK TRIS controls to ‘1’.
Enable the serial port by setting the SPEN bit.
The SYNC bit must be clear for asynchronous
operation.
If interrupts are desired, set the RCIE interrupt
enable bit and set the GIE and PEIE bits of the
INTCON register.
Enable 9-bit reception by setting the RX9 bit.
Enable address detection by setting the ADDEN
bit.
Set the DTRXP if inverted receive polarity is
desired.
Enable reception by setting the CREN bit.
The RCIF interrupt flag bit will be set when a
character with the ninth bit set is transferred
from the RSR to the receive buffer. An interrupt
will be generated if the RCIE interrupt enable bit
was also set.
The ninth data bit will always be set.
from the receive buffer by reading the RCREG
register. Software determines if this is the
device’s address.
clearing the CREN receiver enable bit.
ADDEN bit to allow all received data into the
receive buffer and generate interrupts.
9-bit Address Detection Mode Set-up
2011 Microchip Technology Inc.
Section 18.3 “EUSART
(BRG)”).
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