PIC16LF1904-E/PT Microchip Technology, PIC16LF1904-E/PT Datasheet - Page 116

• Manufacturer Part Number: PIC16LF1904-E/PT
• Description: 7KB Flash, 256B RAM, LCD, 14x10b ADC, EUSART, NanoWatt XLP 44 TQFP 10x10x1mm TRA
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 16Fr

Specifications of PIC16LF1904-E/PT

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: LIN, UART/USART
• Peripherals: Brown-out Detect/Reset, LCD, POR, PWM, WDT
• Number Of I /o: 36
• Program Memory Size: 7KB (4K x 14)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 14x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 44-TQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC16LF1904/6/7
REGISTER 11-20: WPUE: WEAK PULL-UP PORTE REGISTER
TABLE 11-11: SUMMARY OF REGISTERS ASSOCIATED WITH PORTE
DS41569A-page 116
bit 7
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
bit 7-4
bit 3
bit 2-0
Note 1:
ADCON0
ANSELE
LATE
PORTE
TRISE
WPUE
Legend:
Note 1:
Name
U-0
—
2:
2:
Global WPUEN bit of the OPTION_REG register must be cleared for individual pull-ups to be enabled.
The weak pull-up device is automatically disabled if the pin is in configured as an output.
x = unknown, u = unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by PORTE.
Unimplemented, read as ‘1’.
PIC16LF1904/7 only.
Unimplemented: Read as ‘0’
WPUE3: Weak Pull-up Register bit
1 = Pull-up enabled
0 = Pull-up disabled
Unimplemented: Read as ‘0’
Bit 7
—
—
—
—
—
—
U-0
—
Bit 6
—
—
—
—
—
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U-0
—
Bit 5
—
—
—
—
—
CHS<4:0>
U-0
Preliminary
—
Bit 4
—
—
—
—
—
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
WPUE3
R/W-1/1
WPUE3
Bit 3
RE3
—
—
—
(1)
ANSE2
LATE2
RE2
Bit 2
—
—
(2)
(2)
U-0
(2)
—
GO/DONE
ANSE1
LATE1
RE1
Bit 1
 2011 Microchip Technology Inc.
—
—
(2)
(2)
(2)
U-0
—
ANSE0
LATE0
RE0
ADON
Bit 0
—
—
(2)
(2)
(2)
Register
on Page
U-0
—
131
107
114
114
114
116
bit 0