PIC16LF1847T-I/SS Microchip Technology, PIC16LF1847T-I/SS Datasheet - Page 275
PIC16LF1847T-I/SS
Manufacturer Part Number
PIC16LF1847T-I/SS
Description
14 KB Flash, 1K Bytes RAM, 32 MHz Int. Osc, 16 I/0, Enhanced Mid Range Core, Nan
Manufacturer
Microchip Technology
Series
PIC® XLP™ mTouch™ 16Fr
Datasheet
1.PIC16F1847-EP.pdf
(408 pages)
Specifications of PIC16LF1847T-I/SS
Core Processor
PIC
Core Size
8-Bit
Speed
32MHz
Connectivity
I²C, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
15
Program Memory Size
14KB (8K x 14)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
20-SSOP (0.209", 5.30mm Width)
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
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25.6.13.1
During a Start condition, a bus collision occurs if:
a)
b)
During a Start condition, both the SDAx and the SCLx
pins are monitored.
If the SDAx pin is already low, or the SCLx pin is
already low, then all of the following occur:
• the Start condition is aborted,
• the BCLxIF flag is set and
• the MSSPx module is reset to its Idle state
The Start condition begins with the SDAx and SCLx
pins deasserted. When the SDAx pin is sampled high,
the Baud Rate Generator is loaded and counts down. If
the SCLx pin is sampled low while SDAx is high, a bus
collision occurs because it is assumed that another
master is attempting to drive a data ‘1’ during the Start
condition.
FIGURE 25-33:
2011 Microchip Technology Inc.
(Figure
SDAx or SCLx are sampled low at the beginning
of the Start condition
SCLx is sampled low before SDAx is asserted
low
SDAx
SCLx
SEN
BCLxIF
S
SSPxIF
(Figure
25-32).
Bus Collision During a Start
Condition
25-33).
BUS COLLISION DURING START CONDITION (SDAX ONLY)
condition if SDAx = 1, SCLx = 1
Set SEN, enable Start
(Figure
SDAx sampled low before
Start condition. Set BCLxIF.
S bit and SSPxIF set because
SDAx = 0, SCLx = 1.
25-32).
SDAx goes low before the SEN bit is set.
S bit and SSPxIF set because
SDAx = 0, SCLx = 1.
Set BCLxIF,
Preliminary
SSPxIF and BCLxIF are
cleared by software
If the SDAx pin is sampled low during this count, the
BRG is reset and the SDAx line is asserted early
(Figure
SDAx pin, the SDAx pin is asserted low at the end of
the BRG count. The Baud Rate Generator is then
reloaded and counts down to zero; if the SCLx pin is
sampled as ‘0’ during this time, a bus collision does not
occur. At the end of the BRG count, the SCLx pin is
asserted low.
Note:
SEN cleared automatically because of bus collision.
SSPx module reset into Idle state.
25-34). If, however, a ‘1’ is sampled on the
The reason that bus collision is not a fac-
tor during a Start condition is that no two
bus masters can assert a Start condition
at the exact same time. Therefore, one
master will always assert SDAx before the
other. This condition does not cause a bus
collision because the two masters must be
allowed to arbitrate the first address fol-
lowing the Start condition. If the address is
the same, arbitration must be allowed to
continue into the data portion, Repeated
Start or Stop conditions.
SSPxIF and BCLxIF are
cleared by software
PIC16(L)F1847
DS41453B-page 275
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