PIC16LF1827-E/SS Microchip Technology, PIC16LF1827-E/SS Datasheet - Page 97
PIC16LF1827-E/SS
Manufacturer Part Number
PIC16LF1827-E/SS
Description
18 Pin, 7 KB Flash, 384 Bytes RAM, 32 MHz Int. Osc, 16 I/0, Enhanced Mid Range C
Manufacturer
Microchip Technology
Series
PIC® XLP™ 16Fr
Specifications of PIC16LF1827-E/SS
Core Processor
PIC
Core Size
8-Bit
Speed
32MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
16
Program Memory Size
7KB (4K x 14)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
384 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
20-SSOP
Processor Series
PIC16LF
Core
PIC
3rd Party Development Tools
52715-96, 52716-328, 52717-734
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC16LF1827-E/SS
Manufacturer:
MICROCHIP
Quantity:
4 180
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8.5.7
The PIR2 register contains the interrupt flag bits, as
shown in Register 8-7.
REGISTER 8-7:
2010 Microchip Technology Inc.
bit 7
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2-1
bit 0
Note 1:
R/W-0/0
OSFIF
PIC16F/LF1827 only.
PIR2 REGISTER
OSFIF: Oscillator Fail Interrupt Flag bit
1 = Interrupt is pending
0 = Interrupt is not pending
C2IF: Comparator C2 Interrupt Flag bit
1 = Interrupt is pending
0 = Interrupt is not pending
C1IF: Comparator C1 Interrupt Flag bit
1 = Interrupt is pending
0 = Interrupt is not pending
EEIF: EEPROM Write Completion Interrupt Flag bit
1 = Interrupt is pending
0 = Interrupt is not pending
BCL1IF: MSSP1 Bus Collision Interrupt Flag bit
1 = Interrupt is pending
0 = Interrupt is not pending
Unimplemented: Read as ‘0’
CCP2IF: CCP2 Interrupt Flag bit
1 = Interrupt is pending
0 = Interrupt is not pending
R/W-0/0
C2IF
PIR2: PERIPHERAL INTERRUPT REQUEST REGISTER 2
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
R/W-0/0
C1IF
R/W-0/0
(1)
EEIF
Preliminary
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
R/W-0/0
BCL1IF
Note:
PIC16F/LF1826/27
Interrupt flag bits are set when an interrupt
condition occurs, regardless of the state of
its corresponding enable bit or the Global
Enable bit, GIE of the INTCON register.
User
appropriate interrupt flag bits are clear prior
to enabling an interrupt.
U-0
—
software
U-0
should
—
DS41391C-page 97
ensure
CCP2IF
R/W-0/0
bit 0
(1)
the
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