PIC16LF1507-E/SO Microchip Technology, PIC16LF1507-E/SO Datasheet - Page 209
![3.5KB Flash, 128B RAM, 18 I/O, CLC, CWG, DDS, 10-bit ADC 20 SOIC .300in TUBE](/photos/16/12/161297/soic20_sml.jpg)
PIC16LF1507-E/SO
Manufacturer Part Number
PIC16LF1507-E/SO
Description
3.5KB Flash, 128B RAM, 18 I/O, CLC, CWG, DDS, 10-bit ADC 20 SOIC .300in TUBE
Manufacturer
Microchip Technology
Series
PIC® 16Fr
Datasheet
1.PIC16F1507-EML.pdf
(266 pages)
Specifications of PIC16LF1507-E/SO
Processor Series
PIC16
Core
PIC16F
Data Bus Width
8 bit
Program Memory Type
Flash
Program Memory Size
3.5 KB
Data Ram Size
128 B
Interface Type
ICSP
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
18
Number Of Timers
3
Operating Supply Voltage
2.3 V to 5.5 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
Package / Case
SOIC-20
Minimum Operating Temperature
- 40 C
Operating Temperature Range
- 40 C to + 125 C
Supply Current (max)
30 uA
Core Processor
PIC
Core Size
8-Bit
Speed
20MHz
Connectivity
-
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
17
Eeprom Size
-
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Lead Free Status / Rohs Status
Details
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PIC16(L)F1507
TABLE 24-3:
DS41586A-page 209
ADDWF
ADDWFC
ANDWF
ASRF
LSLF
LSRF
CLRF
CLRW
COMF
DECF
INCF
IORWF
MOVF
MOVWF
RLF
RRF
SUBWF
SUBWFB
SWAPF
XORWF
DECFSZ
INCFSZ
BCF
BSF
BTFSC
BTFSS
LITERAL OPERATIONS
ADDLW
ANDLW
IORLW
MOVLB
MOVLP
MOVLW
SUBLW
XORLW
Note 1: If the Program Counter (PC) is modified, or a conditional test is true, the instruction requires two cycles. The second cycle
Mnemonic,
Operands
2: If this instruction addresses an INDF register and the MSb of the corresponding FSR is set, this instruction will require one
is executed as a NOP .
additional instruction cycle.
f, d
f, d
f, d
f, d
f, d
f, d
f
–
f, d
f, d
f, d
f, d
f, d
f
f, d
f, d
f, d
f, d
f, d
f, d
f, d
f, d
f, b
f, b
f, b
f, b
k
k
k
k
k
k
k
k
PIC16(L)F1507 ENHANCED INSTRUCTION SET
Add W and f
Add with Carry W and f
AND W with f
Arithmetic Right Shift
Logical Left Shift
Logical Right Shift
Clear f
Clear W
Complement f
Decrement f
Increment f
Inclusive OR W with f
Move f
Move W to f
Rotate Left f through Carry
Rotate Right f through Carry
Subtract W from f
Subtract with Borrow W from f
Swap nibbles in f
Exclusive OR W with f
Decrement f, Skip if 0
Increment f, Skip if 0
Bit Clear f
Bit Set f
Bit Test f, Skip if Clear
Bit Test f, Skip if Set
Add literal and W
AND literal with W
Inclusive OR literal with W
Move literal to BSR
Move literal to PCLATH
Move literal to W
Subtract W from literal
Exclusive OR literal with W
BYTE-ORIENTED FILE REGISTER OPERATIONS
Description
BIT-ORIENTED FILE REGISTER OPERATIONS
BYTE ORIENTED SKIP OPERATIONS
BIT-ORIENTED SKIP OPERATIONS
Preliminary
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1(2)
1(2)
1
1
1 (2)
1 (2)
1
1
1
1
1
1
1
1
Cycles
00
00
01
01
01
01
11
11
11
00
11
11
11
11
MSb
00
11
00
11
11
11
00
00
00
00
00
00
00
00
00
00
00
11
00
00
14-Bit Opcode
1011
1111
00bb
01bb
10bb
11bb
1110
1001
1000
0000
0001
0000
1100
1010
0111
1101
0101
0111
0101
0110
0001
0001
1001
0011
1010
0100
1000
0000
1101
1100
0010
1011
1110
0110
dfff
dfff
bfff
bfff
bfff
bfff
kkkk
kkkk
kkkk
001k
1kkk
kkkk
kkkk
kkkk
dfff
dfff
dfff
dfff
dfff
dfff
lfff
0000
dfff
dfff
dfff
dfff
dfff
1fff
dfff
dfff
dfff
dfff
dfff
dfff
2011 Microchip Technology Inc.
ffff
ffff
ffff
ffff
ffff
ffff
kkkk
kkkk
kkkk
kkkk
kkkk
kkkk
kkkk
kkkk
ffff
ffff
ffff
ffff
ffff
ffff
ffff
00xx
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
LSb
C, DC, Z
C, DC, Z
Z
C, Z
C, Z
C, Z
Z
Z
Z
Z
Z
Z
Z
C
C
C, DC, Z
C, DC, Z
Z
C, DC, Z
Z
Z
C, DC, Z
Z
Affected
Status
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
1, 2
1, 2
2
2
1, 2
1, 2
Notes
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