PIC16LF1507-E/ML Microchip Technology, PIC16LF1507-E/ML Datasheet - Page 163
![3.5KB Flash, 128B RAM, 18 I/O, CLC, CWG, DDS, 10-bit ADC 20 QFN 4x4mm TUBE](/photos/16/3/160361/qfn20_sml.jpg)
PIC16LF1507-E/ML
Manufacturer Part Number
PIC16LF1507-E/ML
Description
3.5KB Flash, 128B RAM, 18 I/O, CLC, CWG, DDS, 10-bit ADC 20 QFN 4x4mm TUBE
Manufacturer
Microchip Technology
Series
PIC® 16Fr
Datasheet
1.PIC16F1507-EML.pdf
(266 pages)
Specifications of PIC16LF1507-E/ML
Processor Series
PIC16
Core
PIC16F
Data Bus Width
8 bit
Program Memory Type
Flash
Program Memory Size
3.5 KB
Data Ram Size
128 B
Interface Type
ICSP
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
18
Number Of Timers
3
Operating Supply Voltage
2.3 V to 5.5 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
Package / Case
QFN-20
Minimum Operating Temperature
- 40 C
Operating Temperature Range
- 40 C to + 125 C
Supply Current (max)
30 uA
Core Processor
PIC
Core Size
8-Bit
Speed
20MHz
Connectivity
-
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
17
Eeprom Size
-
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Lead Free Status / Rohs Status
Details
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PIC16(L)F1507
20.1.2
Outputs from the input multiplexers are directed to the
desired logic function input through the data gating
stage. Each data gate can direct any combination of the
four selected inputs.
The gate stage is more than just signal direction. The
gate can be configured to direct each input signal as
inverted or non-inverted data. Directed signals are
ANDed together in each gate. The output of each gate
can be inverted before going on to the logic function
stage.
The
AND/NAND/OR/NOR gate. When every input is
inverted and the output is inverted, the gate is an OR of
all enabled data inputs. When the inputs and output are
not inverted, the gate is an AND or all enabled inputs.
Table 20-2
obtained in gate 1 by using the gate logic select bits.
The table shows the logic of four input variables, but
each gate can be configured to use less than four. If
no inputs are selected, the output will be zero or one,
depending on the gate output polarity bit.
TABLE 20-2:
It is possible (but not recommended) to select both the
true and negated values of an input. When this is done,
the gate output is zero, regardless of the other inputs,
but may emit logic glitches (transient-induced pulses).
If the output of the channel must be zero or one, the
recommended method is to set all gate bits to zero and
use the gate polarity bit to set the desired level.
Data gating is configured with the logic gate select reg-
isters as follows:
• Gate 1: CLCxGLS0
• Gate 2: CLCxGLS1
• Gate 3: CLCxGLS2
• Gate 4: CLCxGLS3
Register number suffixes are different than the gate
numbers because other variations of this module have
multiple gate selections in the same register.
DS41586A-page 163
Note:
CLCxGLS0
0xAA
0xAA
0x55
0x55
0x00
0x00
gating
summarizes the basic logic that can be
DATA GATING
Data gating is undefined at power-up.
is
DATA GATING LOGIC
LCxG1POL
in
(Register
(Register
(Register
(Register
1
0
1
0
0
1
essence
20-5)
20-6)
20-7)
20-8)
a
Gate Logic
Logic 0
Logic 1
NAND
1-to-4
NOR
AND
OR
input
Preliminary
Data gating is indicated in the right side of
Only one gate is shown in detail. The remaining three
gates are configured identically with the exception that
the data enables correspond to the enables for that
gate.
20.1.3
There are 8 available logic functions including:
• AND-OR
• OR-XOR
• AND
• S-R Latch
• D Flip-Flop with Set and Reset
• D Flip-Flop with Reset
• J-K Flip-Flop with Reset
• Transparent Latch with Set and Reset
Logic functions are shown in
function has four inputs and one output. The four inputs
are the four data gate outputs of the previous stage.
The output is fed to the inversion stage and from there
to other peripherals, an output pin, and back to the
CLCx itself.
20.1.4
The last stage in the configurable logic cell is the output
polarity. Setting the LCxPOL bit of the CLCxCON reg-
ister inverts the output signal from the logic stage.
Changing the polarity while the interrupts are enabled
will cause an interrupt for the resulting output transition.
LOGIC FUNCTION
OUTPUT POLARITY
2011 Microchip Technology Inc.
Figure
20-3. Each logic
Figure
20-2.
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