PIC16F723-E/SS Microchip Technology, PIC16F723-E/SS Datasheet - Page 5

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PIC16F723-E/SS

Manufacturer Part Number
PIC16F723-E/SS
Description
7 KB Flash, 1.8V-5.5V, 16 MHz Int. Osc. 28 SSOP .209in TUBE
Manufacturer
Microchip Technology
Series
PIC® XLP™ 16Fr

Specifications of PIC16F723-E/SS

Core Processor
PIC
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
25
Program Memory Size
7KB (4K x 14)
Program Memory Type
FLASH
Ram Size
192 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 11x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
28-SSOP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
AC164112 - VOLTAGE LIMITER MPLAB ICD2 VPPAC164307 - MODULE SKT FOR PM3 28SSOP
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PIC16F723-E/SS
Manufacturer:
MICROCHIP
Quantity:
3 190
Part Number:
PIC16F723-E/SS
Manufacturer:
Microchip Technology
Quantity:
135
4. Module: External Oscillator
4.1 Minimum Operating Voltage for HS Mode
5. Module: CPU
5.1 Reset on Wake
6. Module: BOR
6.1 Current Draw in Sleep
 2011 Microchip Technology Inc.
The minimum device V
crystal oscillator in HS mode is 2.7V.
Work around
Use the internal oscillator or an external clock
source if operation below 2.7V is required for the
frequency range supported by HS mode.
Affected Silicon Revisions
If a wake from Sleep event occurs during the
execution of a Sleep command, the device may
reset. This Reset will be seen as a Power-on
Reset to the device.
Work around
1. Disable all asynchronous interrupt before
2. Make sure the timing of an asynchronous
Affected Silicon Revisions
With the BOR set to “Enabled during operation and
disabled during Sleep”, the device draws 2A
more during Sleep than when the BOR is set to
“Disabled”.
Work around
None.
Affected Silicon Revisions
A7
A7
A7
X
X
X
going to Sleep.
interrupt will not happen during the execution
of the Sleep instruction.
A9
A9
A9
X
X
X
AA
AA
AA
X
X
AB
AB
AB
X
X
DD
when using the external
AC
AC
AC
X
AD
AD
AD
X
AK
AK
AK
X
7. Module: WDT
7.1 CLRWDT Instruction after WDT Time-out
8. Module: Interrupts
After a WDT Reset, the TO bit of the STATUS
register remains clear until a SLEEP instruction or
CLRWDT instruction is issued, then, the TO bit will
be set. If the CLRWDT instruction is issued within 20
S of the Reset, the TO bit will remain clear.
Work around
Wait at least 20 S after a WDT Reset before using
the CLRWDT instruction.
Affected Silicon Revisions
The
addresses to the stack when vectoring to the
interrupt vector. Specifically, the interrupt vector
address 0x4 is incorrectly pushed to the stack after
the current PC, at the time the interrupt was
received, is pushed. This will cause the stack to
overflow if the user program is operating seven
calls deep when an interrupt arrives. Because the
stack is circular, the overflow causes the first stack
address to be overwritten.
Work around
Disable interrupts by clearing the GIE bit in the
INTCON register whenever the user program is
operating seven calls deep. This ensures that
interrupts will not cause the stack to overflow.
Affected Silicon Revisions
A7
A7
X
X
interrupt
A9
A9
X
X
AA
AA
PIC16(L)F72X
X
X
logic incorrectly pushes two
AB
AB
X
X
AC
AC
X
X
AD
AD
DS80382J-page 5
X
AK
AK
X

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