PIC16F616-H/SL Microchip Technology, PIC16F616-H/SL Datasheet - Page 21
PIC16F616-H/SL
Manufacturer Part Number
PIC16F616-H/SL
Description
1.75KB Flash, 64B RAM, 6 I/O, 8MHz Internal Oscillator 14 SOIC .150in TUBE
Manufacturer
Microchip Technology
Series
PIC® 16Fr
Datasheets
1.PIC16F616T-ISL.pdf
(4 pages)
2.PIC16F616T-ISL.pdf
(214 pages)
3.PIC16F616T-ISL.pdf
(8 pages)
Specifications of PIC16F616-H/SL
Core Processor
PIC
Core Size
8-Bit
Speed
20MHz
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
11
Program Memory Size
3.5KB (2K x 14)
Program Memory Type
FLASH
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 150°C
Package / Case
14-SOIC (3.9mm Width), 14-SOL
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Connectivity
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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2.2.2.4
The PIE1 register contains the peripheral interrupt
enable bits, as shown in Register 2-4.
REGISTER 2-4:
© 2009 Microchip Technology Inc.
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Note 1:
U-0
—
PIC16F616/16HV616 only. PIC16F610/16HV610 unimplemented, read as ‘0’.
PIE1 Register
Unimplemented: Read as ‘0’
ADIE: A/D Converter (ADC) Interrupt Enable bit
1 = Enables the ADC interrupt
0 = Disables the ADC interrupt
CCP1IE: CCP1 Interrupt Enable bit
1 = Enables the CCP1 interrupt
0 = Disables the CCP1 interrupt
C2IE: Comparator C2 Interrupt Enable bit
1 = Enables the Comparator C2 interrupt
0 = Disables the Comparator C2 interrupt
C1IE: Comparator C1 Interrupt Enable bit
1 = Enables the Comparator C1 interrupt
0 = Disables the Comparator C1 interrupt
Unimplemented: Read as ‘0’
TMR2IE: Timer2 to PR2 Match Interrupt Enable bit
1 = Enables the Timer2 to PR2 match interrupt
0 = Disables the Timer2 to PR2 match interrupt
TMR1IE: Timer1 Overflow Interrupt Enable bit
1 = Enables the Timer1 overflow interrupt
0 = Disables the Timer1 overflow interrupt
ADIE
R/W-0
PIE1: PERIPHERAL INTERRUPT ENABLE REGISTER 1
(1)
W = Writable bit
‘1’ = Bit is set
CCP1IE
R/W-0
(1)
PIC16F610/616/16HV610/616
R/W-0
C2IE
(1)
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
R/W-0
C1IE
(1)
Note:
(1)
Bit PEIE of the INTCON register must be
set to enable any peripheral interrupt.
U-0
—
x = Bit is unknown
TMR2IE
R/W-0
(1)
DS41288F-page 21
TMR1IE
R/W-0
bit 0
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