PIC16F505-I/MG Microchip Technology, PIC16F505-I/MG Datasheet - Page 49
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PIC16F505-I/MG
Manufacturer Part Number
PIC16F505-I/MG
Description
1.5 KB Flash, 72 RAM, 12 I/O 16 QFN 3x3x0.9mm TUBE
Manufacturer
Microchip Technology
Series
PIC® 16Fr
Datasheet
1.PIC12F509T-ISN.pdf
(110 pages)
Specifications of PIC16F505-I/MG
Core Processor
PIC
Core Size
8-Bit
Speed
20MHz
Peripherals
POR, WDT
Number Of I /o
11
Program Memory Size
1.5KB (1K x 12)
Program Memory Type
FLASH
Ram Size
72 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
16-QFN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Connectivity
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
7.3.1
This Configuration bit, when unprogrammed (left in the
‘1’ state), enables the external MCLR function. When
programmed, the MCLR function is tied to the internal
V
Figure 7-6.
FIGURE 7-6:
7.4
The PIC12F508/509/16F505 devices incorporate an
on-chip Power-on Reset (POR) circuitry, which
provides an internal chip Reset for most power-up
situations.
The on-chip POR circuit holds the chip in Reset until
V
operation. To take advantage of the internal POR,
program the (GP3/RB3)/MCLR/V
tie through a resistor to V
(GP3/RB3). An internal weak pull-up resistor is
implemented using a transistor (refer to Table 10-2 for
the pull-up resistor ranges). This will eliminate external
RC components usually needed to create a Power-on
Reset. A maximum rise time for V
Section 10.0 “Electrical Characteristics” for details.
When the devices start normal operation (exit the
Reset
(voltage, frequency, temperature,...) must be met to
ensure operation. If these conditions are not met, the
devices must be held in Reset until the operating
parameters are met.
A simplified block diagram of the on-chip Power-on
Reset circuit is shown in Figure 7-7.
© 2009 Microchip Technology Inc.
MCLRE
DD
DD
GPWU/RBWU
and the pin is assigned to be an input only. See
has reached a high enough level for proper
condition),
Power-on Reset (POR)
MCLR ENABLE
device
MCLR SELECT
DD
, or program the pin as
operating
(GP3/RB3)/MCLR/V
PP
DD
pin as MCLR and
is specified. See
Internal MCLR
parameters
PP
PIC12F508/509/16F505
The Power-on Reset circuit and the Device Reset
Timer (see Section 7.5 “Device Reset Timer (DRT)”)
circuit are closely related. On power-up, the Reset latch
is set and the DRT is reset. The DRT timer begins
counting once it detects MCLR to be high. After the
time-out period, which is typically 18 ms, it will reset the
Reset latch and thus end the on-chip Reset signal.
A power-up example where MCLR is held low is shown
in Figure 7-8. V
bringing MCLR high. The chip will actually come out of
Reset T
In Figure 7-9, the on-chip Power-on Reset feature is
being used (MCLR and V
is programmed to be (GP3/RB3). The V
before the start-up timer times out and there is no prob-
lem in getting a proper Reset. However, Figure 7-10
depicts a problem situation where V
The time between when the DRT senses that MCLR is
high and when MCLR and V
value, is too long. In this situation, when the start-up
timer times out, V
value and the chip may not function correctly. For such
situations, we recommend that external RC circuits be
used to achieve longer POR delay times (Figure 7-9).
For additional information, refer to Application Notes
AN522 “Power-Up Considerations” (DS00522) and
AN607 “Power-up Trouble Shooting” (DS00607).
Note:
DRT
When the devices start normal operation
(exit the Reset condition), device operat-
ing parameters (voltage, frequency, tem-
perature, etc.) must be met to ensure
operation. If these conditions are not met,
the device must be held in Reset until the
operating conditions are met.
msec after MCLR goes high.
DD
is allowed to rise and stabilize before
DD
has not reached the V
DD
are tied together or the pin
DD
actually reach their full
DD
DS41236E-page 49
rises too slowly.
DD
is stable
DD
(min)