PIC16F1934-E/P Microchip Technology, PIC16F1934-E/P Datasheet - Page 4

• Manufacturer Part Number: PIC16F1934-E/P
• Description: 7KB Flash, 256B RAM, 256B EEPROM, LCD, 1.8-5.5V 40 PDIP .600in TUBE
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 16Fr

Specifications of PIC16F1934-E/P

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 32MHz
• Connectivity: I²C, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LCD, POR, PWM, WDT
• Number Of I /o: 36
• Program Memory Size: 7KB (4K x 14)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 14x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 40-DIP (0.600", 15.24mm)
• Processor Series: PIC16F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: EUSART, MI2C, SPI
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 36
• Number Of Timers: 5
• Maximum Operating Temperature: + 125 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 14 Channel
• A/d Bit Size: 10 bit
• A/d Channels Available: 14
• Height: 4.95 mm
• Length: 53.21 mm
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 1.8 V
• Width: 14.73 mm
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PIC16F1934/1936/1937 and PIC16LF1934/1936/1937
3.4 Capture mode Selected while CCPx Pin is
3.5 ECCPx Dead Time Delay in Half-Bridge mode
3.6 PWM with Pulse Steering
3.7 Capture mode Selected while CCPx Pin is
DS80479F-page 4
Held High
If the module is configured to capture on the first
rising edge and the CCPx pin is high at this time, a
capture will be triggered.
Work around
Clear the CCP interrupt flag (CCPxIF
immediately after configuring the module for a cap-
ture event.
Affected Silicon Revisions
In Half-Bridge mode the dead band delay is 1 T
longer than calculated for the first PWM cycle and
1.5 T
Work around
None.
Affected Silicon Revisions
Disabling a PWM output during a PWM cycle will
cause the output to end one T
expected.
Work around
None.
Affected Silicon Revisions
Held Low
If the module is configured to capture on the first
falling edge and the CCPx pin is low at this time, a
capture will be triggered.
Work around
Clear the CCP interrupt flag (CCPxIF
immediately after configuring the module for a cap-
ture event.
Affected Silicon Revisions
A2
A2
A2
A2
X
X
X
X
OSC
A3
A3
A3
A3
X
X
X
X
for following cycles.
A5
A5
A5
A5
X
X
X
X
A6
A6
A6
A6
X
X
X
X
OSC
time earlier than
=
=
OSC
0)
0)
4. Module: Brown-Out Reset (BOR)
4.1 Brown-Out Threshold
Configuring the BOR for 2.5V operation, the reset
will typically occur at 2.7V.
Work around
None.
Affected Silicon Revisions
A2
X
A3
A5
 2010 Microchip Technology Inc.
A6