PIC16F1934-E/MV Microchip Technology, PIC16F1934-E/MV Datasheet - Page 290

• Manufacturer Part Number: PIC16F1934-E/MV
• Description: 7KB Flash, 256B RAM, 256B EEPROM, LCD, 1.8-5.5V 40 UQFN 5x5x0.5mm TUBE
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 16Fr

Specifications of PIC16F1934-E/MV

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 32MHz
• Connectivity: I²C, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LCD, POR, PWM, WDT
• Number Of I /o: 36
• Program Memory Size: 7KB (4K x 14)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 14x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 40-UFQFN Exposed Pad
• Processor Series: PIC16F
• Core: PIC
• Data Ram Size: 256 B
• Interface Type: MI2C, SPI, EUSART
• Number Of Timers: 5
• Operating Supply Voltage: 1.8 V to 5.5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: MPLAB IDE Software
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PIC16F193X/LF193X
FIGURE 24-2:
The operation of the EUSART module is controlled
through three registers:
• Transmit Status and Control (TXSTA)
• Receive Status and Control (RCSTA)
• Baud Rate Control (BAUDCON)
These
Register 24-2 and Register 24-3, respectively.
When the receiver or transmitter section is not enabled
then the corresponding RX or TX pin may be used for
general purpose input and output.
DS41364D-page 290
BRG16
Baud Rate Generator
SPBRGH
registers
SPBRGL
RX/DT pin
are
+ 1
EUSART RECEIVE BLOCK DIAGRAM
detailed
Multiplier
BRG16
SYNC
BRGH
Pin Buffer
and Control
in
SPEN
1 X 0 0
X 1 1 0
X 1 0 1
x4
Register 24-1,
x16 x64
F
OSC
0
0
0
Preliminary
n
Data
Recovery
÷ n
FERR
Stop
MSb
CREN
(8)
RX9D
7
RX9
RSR Register
 2009 Microchip Technology Inc.
RCREG Register
• • •
OERR
8
1
RCIF
RCIE
Data Bus
0
START
LSb
RCIDL
Interrupt
FIFO