PIC16F1823-I/SL Microchip Technology, PIC16F1823-I/SL Datasheet - Page 305
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PIC16F1823-I/SL
Manufacturer Part Number
PIC16F1823-I/SL
Description
3.5 KB Flash, 128 Bytes RAM, 32 MHz Int. Osc, 12 I/0, Enhanced Mid Range Core 14
Manufacturer
Microchip Technology
Series
PIC® XLP™ 16Fr
Datasheets
1.PIC16F722-ISS.pdf
(8 pages)
2.PIC12F1822T-ISN.pdf
(404 pages)
3.PIC12F1822T-ISN.pdf
(10 pages)
Specifications of PIC16F1823-I/SL
Core Processor
PIC
Core Size
8-Bit
Speed
32MHz
Connectivity
I²C, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
12
Program Memory Size
3.5KB (2K x 14)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
14-SOIC (3.9mm Width), 14-SOL
Core
PIC
Processor Series
PIC16F
Data Bus Width
8 bit
Maximum Clock Frequency
32 MHz
Data Ram Size
128 B
On-chip Adc
Yes
Number Of Programmable I/os
12
Number Of Timers
3
Operating Supply Voltage
2.3 V to 5.5 V
Operating Temperature Range
- 40 C to + 85 C
A/d Bit Size
10 bit
A/d Channels Available
8
Height
1.25 mm
Interface Type
I2C, SPI, USART
Length
8.65 mm
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
Supply Voltage (max)
5.5 V
Supply Voltage (min)
2.3 V
Width
3.9 mm
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC16F1823-I/SL
Manufacturer:
MICROCHIP
Quantity:
30 000
Part Number:
PIC16F1823-I/SL
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
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26.3.4
The EUSART module has the capability of sending the
special Break character sequences that are required by
the LIN bus standard. A Break character consists of a
Start bit, followed by 12 ‘0’ bits and a Stop bit.
To send a Break character, set the SENDB and TXEN
bits of the TXSTA register. The Break character trans-
mission is then initiated by a write to the TXREG. The
value of data written to TXREG will be ignored and all
‘0’s will be transmitted.
The SENDB bit is automatically reset by hardware after
the corresponding Stop bit is sent. This allows the user
to preload the transmit FIFO with the next transmit byte
following the Break character (typically, the Sync
character in the LIN specification).
The TRMT bit of the TXSTA register indicates when the
transmit operation is active or Idle, just as it does during
normal transmission. See
the Break character sequence.
26.3.4.1
The following sequence will start a message frame
header made up of a Break, followed by an auto-baud
Sync byte. This sequence is typical of a LIN bus
master.
1.
2.
3.
4.
5.
When the TXREG becomes empty, as indicated by the
TXIF, the next data byte can be written to TXREG.
FIGURE 26-9:
2010 Microchip Technology Inc.
Write to TXREG
(Transmit Shift
Configure the EUSART for the desired mode.
Set the TXEN and SENDB bits to enable the
Break sequence.
Load the TXREG with a dummy character to
initiate transmission (the value is ignored).
Write ‘55h’ to TXREG to load the Sync character
into the transmit FIFO buffer.
After the Break has been sent, the SENDB bit is
reset by hardware and the Sync character is
then transmitted.
Interrupt Flag)
(send Break
BRG Output
(Shift Clock)
Empty Flag)
control bit)
(Transmit
TRMT bit
TX (pin)
TXIF bit
SENDB
BREAK CHARACTER SEQUENCE
Break and Sync Transmit Sequence
SEND BREAK CHARACTER SEQUENCE
Dummy Write
Figure 26-9
SENDB Sampled Here
PIC12F/LF1822/PIC16F/LF1823
Start bit
for the timing of
bit 0
Preliminary
bit 1
Break
26.3.5
The Enhanced EUSART module can receive a Break
character in two ways.
The first method to detect a Break character uses the
FERR bit of the RCSTA register and the Received data
as indicated by RCREG. The Baud Rate Generator is
assumed to have been initialized to the expected baud
rate.
A Break character has been received when;
• RCIF bit is set
• FERR bit is set
• RCREG = 00h
The second method uses the Auto-Wake-up feature
described in
Break”. By enabling this feature, the EUSART will
sample the next two transitions on RX/DT, cause an
RCIF interrupt, and receive the next data byte followed
by another interrupt.
Note that following a Break character, the user will
typically want to enable the Auto-Baud Detect feature.
For both methods, the user can set the ABDEN bit of
the BAUDCON register before placing the EUSART in
Sleep mode.
RECEIVING A BREAK CHARACTER
Section 26.3.3 “Auto-Wake-up on
bit 11
Auto Cleared
Stop bit
DS41413B-page 305
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