PIC16C72A-20/SS Microchip Technology, PIC16C72A-20/SS Datasheet - Page 9
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PIC16C72A-20/SS
Manufacturer Part Number
PIC16C72A-20/SS
Description
IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,SSOP,28PIN,PLASTIC
Manufacturer
Microchip Technology
Series
PIC® 16Cr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC16F818-ISO.pdf
(6 pages)
3.PIC16C62B-04SO.pdf
(120 pages)
4.PIC16C72A-04SP.pdf
(6 pages)
Specifications of PIC16C72A-20/SS
Rohs Compliant
YES
Core Processor
PIC
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, SPI
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
22
Program Memory Size
3.5KB (2K x 14)
Program Memory Type
OTP
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
4 V ~ 5.5 V
Data Converters
A/D 5x8b
Oscillator Type
External
Operating Temperature
0°C ~ 70°C
Package / Case
28-SSOP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
309-1025 - ADAPTER 28-SSOP TO 28-DIP
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC16C72A-20/SS
Manufacturer:
MICROCHIP
Quantity:
125
Part Number:
PIC16C72A-20/SS
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
2.2.2
The Special Function Registers are registers used by
the CPU and Peripheral Modules for controlling the
desired operation of the device. These registers are
implemented as static RAM. A list of these registers is
given in Table 2-1.
TABLE 2-1
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ’0’,
Note 1: These registers can be addressed from either bank.
00h
01h
02h
03h
04h
05h
06h
07h
08h-09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
12h
13h
14h
15h
16h
17h
18h-1Dh
1Eh
1Fh
1999 Microchip Technology Inc.
Bank 0
Addr
2: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for PC<12:8> whose contents
3: A/D not implemented on the PIC16C62B, maintain as ’0’.
4: Other (non power-up) resets include: external reset through MCLR and the Watchdog Timer Reset.
5: The IRP and RP1 bits are reserved. Always maintain these bits clear.
6: On any device reset, these pins are configured as inputs.
7: This is the value that will be in the port output latch.
SPECIAL FUNCTION REGISTERS
Shaded locations are unimplemented, read as ’0’.
are transferred to the upper byte of the program counter.
INDF
TMR0
PCL
STATUS
FSR
PORTA
PORTB
PORTC
PCLATH
INTCON
PIR1
TMR1L
TMR1H
T1CON
TMR2
T2CON
SSPBUF
SSPCON
CCPR1L
CCPR1H
CCP1CON
ADRES
ADCON0
Name
(1)
(1)
(1)
—
—
—
(6,7)
(6,7)
(6,7)
(3)
(1)
(1,2)
(1)
(3)
SPECIAL FUNCTION REGISTER SUMMARY
Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 0000 0000
Timer0 module’s register
Program Counter's (PC) Least Significant Byte
Indirect data memory address pointer
PORTB Data Latch when written: PORTB pins when read
PORTC Data Latch when written: PORTC pins when read
Unimplemented
Unimplemented
Holding register for the Least Significant Byte of the 16-bit TMR1 register
Holding register for the Most Significant Byte of the 16-bit TMR1 register
Timer2 module’s register
Synchronous Serial Port Receive Buffer/Transmit Register
Capture/Compare/PWM Register1 (LSB)
Capture/Compare/PWM Register1 (MSB)
Unimplemented
A/D Result Register
ADCS1
WCOL
IRP
Bit 7
GIE
—
—
—
—
—
—
(5)
TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0
ADIF
SSPOV
ADCS0
RP1
Bit 6
PEIE
—
—
—
—
(5)
(3)
PORTA Data Latch when written: PORTA pins when read
T1CKPS1 T1CKPS0 T1OSCEN
SSPEN
CCP1X
CHS2
Bit 5
T0IE
RP0
—
—
Write Buffer for the upper 5 bits of the Program Counter
Preliminary
CCP1Y
CHS1
INTE
Bit 4
CKP
TO
—
CCP1M3
SSPM3
SSPIF
CHS0
RBIE
Bit 3
PD
The Special Function Registers can be classified into
two sets; core (CPU) and peripheral. Those registers
associated with the core functions are described in
detail in this section. Those related to the operation of
the peripheral features are described in detail in the
peripheral feature section.
GO/DONE
TMR2ON
T1SYNC
CCP1M2
CCP1IF
SSPM2
Bit 2
T0IF
Z
PIC16C62B/72A
T2CKPS1 T2CKPS0 -000 0000 -000 0000
TMR1CS
CCP1M1
TMR2IF
SSPM1
INTF
Bit 1
DC
—
TMR1ON --00 0000 --uu uuuu
CCP1M0
TMR1IF
SSPM0
ADON
Bit 0
RBIF
C
xxxx xxxx uuuu uuuu
0000 0000 0000 0000
0001 1xxx 000q quuu
xxxx xxxx uuuu uuuu
--0x 0000 --0u 0000
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
---0 0000 ---0 0000
0000 000x 0000 000u
-0-- 0000 -0-- 0000
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
0000 0000 0000 0000
xxxx xxxx uuuu uuuu
0000 0000 0000 0000
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
--00 0000 --00 0000
xxxx xxxx uuuu uuuu
0000 00-0 0000 00-0
Value on:
DS35008B-page 9
POR,
BOR
—
—
—
other resets
Value on all
(4)
—
—
—