PIC12LF1840T-I/SN Microchip Technology, PIC12LF1840T-I/SN Datasheet - Page 145
![7 KB Flash, 256 Bytes RAM, 32 MHz Int. Osc, 6 I/0, Enhanced Mid Range Core, Nano](/photos/16/3/160347/soic8_sml.jpg)
PIC12LF1840T-I/SN
Manufacturer Part Number
PIC12LF1840T-I/SN
Description
7 KB Flash, 256 Bytes RAM, 32 MHz Int. Osc, 6 I/0, Enhanced Mid Range Core, Nano
Manufacturer
Microchip Technology
Series
PIC® XLP™ 12Fr
Datasheet
1.PIC12F1840-EMF.pdf
(382 pages)
Specifications of PIC12LF1840T-I/SN
Processor Series
PIC12F
Core
PIC
Program Memory Type
Flash
Program Memory Size
7 KB
Data Ram Size
256 B
Interface Type
MI2C, SPI, EUSART
Number Of Timers
3
Operating Supply Voltage
1.8 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Package / Case
SOIC-8
Development Tools By Supplier
MPLAB IDE Software
Minimum Operating Temperature
- 40 C
Core Processor
RISC
Core Size
8-Bit
Speed
32MHz
Connectivity
I²C, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
5
Eeprom Size
256 x 8
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC12LF1840T-I/SN
Manufacturer:
ST
Quantity:
2 400
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18.0
The module consists of a single SR Latch with multiple
Set and Reset inputs as well as separate latch outputs.
The SR Latch module includes the following features:
• Programmable input selection
• SR Latch output is available externally
• Separate Q and Q outputs
• Firmware Set and Reset
The SR Latch can be used in a variety of analog appli-
cations, including oscillator circuits, one-shot circuit,
hysteretic controllers, and analog timing applications.
18.1
The latch is a Set-Reset Latch that does not depend on
a clock source. Each of the Set and Reset inputs are
active-high. The latch can be Set or Reset by:
• Software control (SRPS and SRPR bits)
• Comparator C1 output (SYNCC1OUT)
• SRI pin
• Programmable clock (SRCLK)
The SRPS and the SRPR bits of the SRCON0 register
may be used to Set or Reset the SR Latch, respec-
tively. The latch is Reset-dominant. Therefore, if both
Set and Reset inputs are high, the latch will go to the
Reset state. Both the SRPS and SRPR bits are self
resetting which means that a single write to either of the
bits is all that is necessary to complete a latch Set or
Reset operation.
The output from Comparator C1 can be used as the Set
or Reset inputs of the SR Latch. The output of the
Comparator can be synchronized to the Timer1 clock
source. See Section 19.0 “Comparator Module” and
Section 21.0 “Timer1 Module with Gate Control” for
more information.
An external source on the SRI pin can be used as the
Set or Reset inputs of the SR Latch.
An internal clock source is available that can periodically
set or reset the SR Latch. The SRCLK<2:0> bits in the
SRCON0 register are used to select the clock source
period. The SRSCKE and SRRCKE bits of the SRCON1
register enable the clock source to Set or Reset the SR
Latch, respectively.
18.2
The SRQEN and SRNQEN bits of the SRCON0 regis-
ter control the Q and Q latch outputs. Both of the SR
Latch outputs may be directly output to an I/O pin at the
same time.
2011 Microchip Technology Inc.
Note:
SR LATCH
Latch Operation
Latch Output
Enabling both the Set and Reset inputs
from any one source at the same time
may result in indeterminate operation, as
the Reset dominance cannot be assured.
Preliminary
The applicable TRIS bit of the corresponding port must
be cleared to enable the port pin output driver.
18.3
Upon any device Reset, the SR Latch output is not ini-
tialized to a known state. The user’s firmware is
responsible for initializing the latch output before
enabling the output pins.
Effects of a Reset
PIC12(L)F1840
DS41441B-page 145
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