PIC12LF1822T-I/SN Microchip Technology, PIC12LF1822T-I/SN Datasheet - Page 207

• Manufacturer Part Number: PIC12LF1822T-I/SN
• Description: 3.5 KB Flash, 128 Bytes RAM, 32 MHz Int. Osc, 6 I/0, Enhanced Mid Range Core, Na
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 12Fr

Specifications of PIC12LF1822T-I/SN

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 32MHz
• Connectivity: I²C, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 6
• Program Memory Size: 3.5KB (2K x 14)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-SOIC (3.9mm Width)
• Processor Series: PIC12LF
• Core: PIC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

24.2.5
The Compare mode is dependent upon the system
clock (F
down during Sleep mode, the Compare mode will not
function properly during Sleep.
TABLE 24-4:
 2010 Microchip Technology Inc.
APFCON
CCP1CON
CCPR1L
CCPR1H
INTCON
PIE1
PIE2
PIR1
PIR2
T1CON
T1GCON
TMR1H
TMR1L
TRISA
TRISC
Legend: — = Unimplemented location, read as ‘0’. Shaded cells are not used by Compare mode.
Note 1:
Name
(1)
OSC
PIC16F/LF1823 only.
COMPARE DURING SLEEP
) for proper operation. Since F
Capture/Compare/PWM Register 1 Low Byte (LSB)
Capture/Compare/PWM Register 1 High Byte (MSB)
Holding Register for the Most Significant Byte of the 16-bit TMR1 Register
Holding Register for the Least Significant Byte of the 16-bit TMR1 Register
RXDTSEL
TMR1GIE
TMR1GIF
TMR1GE
OSFIE
OSFIF
Bit 7
GIE
TMR1CS<1:0>
—
—
SUMMARY OF REGISTERS ASSOCIATED WITH COMPARE
P1M<1:0>
SDOSEL
T1GPOL
C2IE
C2IF
PEIE
ADIE
ADIF
Bit 6
—
—
(1)
(1)
TMR0IE
TRISC5
T1GTM
TRISA5
SSSEL
PIC12F/LF1822/PIC16F/LF1823
RCIE
RCIF
C1IE
Bit 5
C1IF
T1CKPS<1:0>
DC1B<1:0>
OSC
T1GSPM
is shut
TRISA4
TRISC4
INTE
EEIE
Bit 4
TXIE
TXIF
EEIF
—
Preliminary
T1GGO/DONE
T1OSCEN
T1GSEL
SSP1IE
TRISA3
TRISC3
BCL1IE
SSP1IF
BCL1IF
IOCIE
Bit 3
24.2.6
This module incorporates I/O pins that can be moved to
other locations with the use of the alternate pin function
register, APFCON. To determine which pins can be
moved and what their default locations are upon a
Reset, see
more information.
TXCKSEL
T1SYNC
T1GVAL
TMR0IF
CCP1IE
CCP1IF
TRISC2
TRISA2
Section 12.1 “Alternate Pin Function”
ALTERNATE PIN LOCATIONS
Bit 2
CCP1M<3:0>
—
—
P1BSEL
TMR2IE
TMR2IF
TRISC1
TRISA1
INTF
Bit 1
—
—
—
T1GSS<1:0>
CCP1SEL
TMR1ON
TMR1IE
TMR1IF
TRISA0
TRISC0
IOCIF
Bit 0
DS41413B-page 207
—
—
Register
on Page
121
226
204
204
185
186
181
181
124
128
91
92
93
94
95
for