PIC12F617T-I/SN Microchip Technology, PIC12F617T-I/SN Datasheet - Page 21
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PIC12F617T-I/SN
Manufacturer Part Number
PIC12F617T-I/SN
Description
3.5KB Self Read/Write Flash, 128B RAM, 6 I/O, 8MHz Internal Oscillator 8 SOIC 3.
Manufacturer
Microchip Technology
Series
PIC® 12Fr
Datasheets
1.PIC12F609T-ISN.pdf
(212 pages)
2.PIC12F609T-ISN.pdf
(8 pages)
3.PIC12F617-IP.pdf
(4 pages)
Specifications of PIC12F617T-I/SN
Core Processor
PIC
Core Size
8-Bit
Speed
20MHz
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
5
Program Memory Size
3.5KB (2K x 14)
Program Memory Type
FLASH
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
8-SOIC (3.9mm Width)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Connectivity
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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2.2.2.4
The PIE1 register contains the Peripheral Interrupt
Enable bits, as shown in Register 2-4.
REGISTER 2-4:
2010 Microchip Technology Inc.
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Note 1: PIC12F615/617/HV615 only. PIC12F609/HV609 unimplemented, read as ‘0’.
U-0
—
PIE1 Register
Unimplemented: Read as ‘0’
ADIE: A/D Converter (ADC) Interrupt Enable bit
1 = Enables the ADC interrupt
0 = Disables the ADC interrupt
CCP1IE: CCP1 Interrupt Enable bit
1 = Enables the CCP1 interrupt
0 = Disables the CCP1 interrupt
Unimplemented: Read as ‘0’
CMIE: Comparator Interrupt Enable bit
1 = Enables the Comparator interrupt
0 = Disables the Comparator interrupt
Unimplemented: Read as ‘0’
TMR2IE: Timer2 to PR2 Match Interrupt Enable bit
1 = Enables the Timer2 to PR2 match interrupt
0 = Disables the Timer2 to PR2 match interrupt
TMR1IE: Timer1 Overflow Interrupt Enable bit
1 = Enables the Timer1 overflow interrupt
0 = Disables the Timer1 overflow interrupt
ADIE
R/W-0
PIE1: PERIPHERAL INTERRUPT ENABLE REGISTER 1
(1)
W = Writable bit
‘1’ = Bit is set
CCP1IE
PIC12F609/615/617/12HV609/615
R/W-0
(1)
U-0
—
(1)
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
R/W-0
CMIE
(1)
Note:
(1)
Bit PEIE of the INTCON register must be
set to enable any peripheral interrupt.
U-0
—
x = Bit is unknown
TMR2IE
R/W-0
(1)
DS41302D-page 21
TMR1IE
R/W-0
bit 0
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