PIC12F1822T-I/MF Microchip Technology, PIC12F1822T-I/MF Datasheet - Page 371
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PIC12F1822T-I/MF
Manufacturer Part Number
PIC12F1822T-I/MF
Description
3.5 KB Flash, 128 Bytes RAM, 32 MHz Int. Osc, 6 I/0, Enhanced Mid Range Core 8 D
Manufacturer
Microchip Technology
Series
PIC® XLP™ 12Fr
Specifications of PIC12F1822T-I/MF
Core Processor
PIC
Core Size
8-Bit
Speed
32MHz
Connectivity
I²C, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
6
Program Memory Size
3.5KB (2K x 14)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
8-DFN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PIC12F1822T-I/MF
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
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TABLE 30-15: I
2010 Microchip Technology Inc.
Note 1:
SP100* T
SP101* T
SP102* T
SP103* T
SP106* T
SP107* T
SP109* T
Param.
SP110* T
SP111
No.
2:
*
These parameters are characterized but not tested.
As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region
(min. 300 ns) of the falling edge of SCLx to avoid unintended generation of Start or Stop conditions.
A Fast mode (400 kHz) I
the requirement T
not stretch the low period of the SCLx signal. If such a device does stretch the low period of the SCLx sig-
nal, it must output the next data bit to the SDAx line T
to the Standard mode I
C
Symbol
SU
AA
HIGH
LOW
R
F
HD
BUF
B
:
:
DAT
DAT
2
C™ BUS DATA REQUIREMENTS
Clock high time
Clock low time
SDAx and SCLx
rise time
SDAx and SCLx fall
time
Data input hold time 100 kHz mode
Data input setup
time
Output valid from
clock
Bus free time
Bus capacitive loading
SU
:
DAT
Characteristic
2
C bus specification), before the SCLx line is released.
2
250 ns must then be met. This will automatically be the case if the device does
C
PIC12F/LF1822/PIC16F/LF1823
™
bus device can be used in a Standard mode (100 kHz) I
100 kHz mode
400 kHz mode
SSPx module
100 kHz mode
400 kHz mode
SSPx module
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
Preliminary
20 + 0.1C
20 + 0.1C
1.5T
1.5T
R
Min.
250
100
4.0
0.6
4.7
1.3
4.7
1.3
max. + T
—
—
—
—
—
0
0
CY
CY
B
B
SU
Max.
1000
3500
300
250
250
0.9
400
—
—
—
—
—
—
—
—
—
—
—
—
:
DAT
= 1000 + 250 = 1250 ns (according
Units
s
s
s
s
ns
ns
ns
ns
ns
s
ns
ns
ns
ns
s
s
pF
—
—
Device must operate at a
minimum of 1.5 MHz
Device must operate at a
minimum of 10 MHz
Device must operate at a
minimum of 1.5 MHz
Device must operate at a
minimum of 10 MHz
C
10-400 pF
C
10-400 pF
(Note 2)
(Note 1)
Time the bus must be free
before a new transmission
can start
B
B
is specified to be from
is specified to be from
2
Conditions
C bus system, but
DS41413B-page 371
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