PIC12F1822-E/MF Microchip Technology, PIC12F1822-E/MF Datasheet - Page 242

• Manufacturer Part Number: PIC12F1822-E/MF
• Description: 3.5 KB Flash, 128 Bytes RAM, 32 MHz Int. Osc, 6 I/0, Enhanced Mid Range Core 8 D
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 12Fr

Specifications of PIC12F1822-E/MF

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 32MHz
• Connectivity: I²C, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 6
• Program Memory Size: 3.5KB (2K x 14)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 8-DFN
• Processor Series: PIC12F
• Core: PIC
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734
• Development Tools By Supplier: ICE2000
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PIC12F/LF1822/PIC16F/LF1823
25.2.6
In SPI Master mode, module clocks may be operating
at a different speed than when in full power mode; in
the case of the Sleep mode, all clocks are halted.
Special care must be taken by the user when the
MSSP1 clock is much faster than the system clock.
In Slave mode, when MSSP1 interrupts are enabled,
after the master completes sending data, an MSSP1
interrupt will wake the controller from Sleep.
If an exit from Sleep mode is not desired, MSSP1
interrupts should be disabled.
TABLE 25-1:
DS41413B-page 242
ANSELA
ANSELC
APFCON
INTCON
PIE1
PIR1
SSP1BUF
SSP1CON1
SSP1CON3
SSP1STAT
TRISA
TRISC
Legend:
Note 1:
Name
*
SPI OPERATION IN SLEEP MODE
— = Unimplemented location, read as ‘0’. Shaded cells are not used by the MSSP1 in SPI mode.
Page provides register information.
PIC16F/LF1823 only.
Synchronous Serial Port Receive Buffer/Transmit Register
RXDTSEL
TMR1GIE
TMR1GIF
ACKTIM
WCOL
Bit 7
SMP
GIE
—
—
—
—
SUMMARY OF REGISTERS ASSOCIATED WITH SPI OPERATION
SDOSEL
SSPOV
PEIE
ADIE
ADIF
PCIE
Bit 6
CKE
—
—
—
—
TMR0IE
TRISC5
SSPEN
TRISA5
SSSEL
RCIE
RCIF
SCIE
Bit 5
D/A
—
—
TRISA4
TRISC4
ANSA4
BOEN
Preliminary
INTE
Bit 4
TXIE
TXIF
CKP
—
—
P
T1GSEL
SSP1IE
TRISA3
TRISC3
ANSC3
SSP1IF
SDAHT
IOCIE
Bit 3
In SPI Master mode, when the Sleep mode is selected,
all module clocks are halted and the transmis-
sion/reception will remain in that state until the device
wakes. After the device returns to Run mode, the mod-
ule will resume transmitting and receiving data.
In SPI Slave mode, the SPI Transmit/Receive Shift
register operates asynchronously to the device. This
allows the device to be placed in Sleep mode and data
to be shifted into the SPI Transmit/Receive Shift
register. When all 8 bits have been received, the
MSSP1 interrupt flag bit will be set and if enabled, will
wake the device.
—
S
TXCKSEL
TMR0IF
CCP1IE
CCP1IF
SBCDE
TRISA2
TRISC2
ANSA2
ANSC2
Bit 2
R/W
SSPM<3:0>
P1BSEL
TMR2IE
TMR2IF
TRISC1
TRISA1
ANSA1
ANSC1
AHEN
Bit 1
INTF
 2010 Microchip Technology Inc.
UA
CCP1SEL
TMR1IE
TMR1IF
TRISA0
TRISC0
ANSC0
ANSA0
DHEN
IOCIF
Bit 0
BF
Register
on Page
235*
125
129
121
281
283
280
124
128
91
92
94