LMP90100MHE National Semiconductor, LMP90100MHE Datasheet
LMP90100MHE
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LMP90100MHE Summary of contents
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... Typical Application TRI-STATE ® registered trademark of National Semiconductor Corporation. © 2011 National Semiconductor Corporation LMP90100 ■ 2 matched excitation current sources from 100 µA to 1000 µA ■ 4-DIFF / 7-SE flexible and programmable MUX channels ■ ...
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Block Diagram • True Continuous Background Calibration The LMP90100 features a 24 bit ΣΔ core with continuous background calibration to compensate for gain and offset er- rors in the ADC, virtually eliminating any drift with time and temperature. The ...
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General Description ......................................................................................................................... 1 2.0 Features ........................................................................................................................................ 1 3.0 Key Specifications ........................................................................................................................... 1 4.0 Applications .................................................................................................................................... 1 5.0 Typical Application ........................................................................................................................... 1 6.0 Block Diagram ................................................................................................................................ 2 7.0 Ordering Information ........................................................................................................................ 5 8.0 Connection Diagram ........................................................................................................................ 5 9.0 Pin ...
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Sensor Diagnostic Registers .................................................................................................. 54 18.7 SPI Registers ....................................................................................................................... 55 18.8 GPIO Registers .................................................................................................................... 57 19.0 Physical Dimensions .................................................................................................................... 58 FIGURE 1. Block Diagram ......................................................................................................................... 2 FIGURE 2. Timing Diagram ...................................................................................................................... 11 FIGURE 3. Simplified VIN Circuitry .............................................................................................................. 21 ...
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... Ordering Information Order Code LMP90100MH/NOPB LMP90100MHE/NOPB LMP90100MHX/NOPB 8.0 Connection Diagram 9.0 Pin Descriptions Pin # Pin Name VIN0 - VIN5 8 VREFP1 9 VREFN1 10 VIN6 / VREFP2 11 VIN7 / VREFN2 IB2 & IB1 14 XOUT 15 XIN / CLK 16 GND 17 CSB 18 SCLK 19 SDI 20 SDO / DRDYB DRDYB 28 VIO Temperature Range − ...
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... Absolute Maximum Ratings 1, Note 2) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Analog Supply Voltage, VA Digital I/O Supply Voltage, VIO Reference Voltage, VREF Voltage on Any Analog Input Pin to GND (Note ...
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Symbol Parameter 3V & 214. & 13. Gain Error 3V & 13. & ...
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Symbol Parameter REFERENCE INPUT VREFP Positive Reference Negative VREFN Reference Differential VREF VREF = VREFP - VREFN Reference Reference ZREF 3V / 13.42 / OFF / OFF / 1 Impedance 3V / 13. OFF / ON or ...
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Symbol Parameter EXCITATION CURRENT SOURCES CHARACTERISTICS Excitation Current IB1, IB2 Source Output VA = VREF = 3V IB1/IB2 Tolerance VA = VREF = 5V IB1/IB2 Output VA = 3.0V & 5.0V, Compliance Range IB1/IB2 = 100 µA to 1000 µA ...
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TABLE 1. ENOB (Noise Free Resolution) vs. Sampling Rate and Gain VIO = VREF = 3V ODR (SPS) 1 1.6775 20.5 (18) 20.5 (18) 3.355 20 (17.5) 20 (17.5) 6.71 19.5 (17) 19.5 (17) 13.42 19 (16.5) ...
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Timing Diagrams Unless otherwise noted, specified limits apply for VA = VIO = 3.0V. Boldface limits apply for T apply for T = +25°C. A Symbol Parameter f SCLK t SCLK High time CH t SCLK Low time CL ...
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Symbol Parameter t SCLK Rise time CLKR t SCLK Fall time CLKF SDI Setup time prior to an SCLK t rising edge DISU SDI Hold time after an SCLK rising t edge DIH Symbol Parameter SDO Access time after an ...
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Symbol Parameter SDO Disable time after either t DOD2 edge of SCLK Symbol Parameter SDO Enable time from the falling t DOE edge of the 8th SCLK t SDO Rise time DOR t SDO Fall time DOF Data Ready Bar ...
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Specific Definitions COMMON MODE REJECTION RATIO is a measure of how well in-phase signals common to both input pins are rejected. To calculate CMRR, the change in output offset is measured while the common mode input voltage is changed. ...
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Typical Performance Characteristics VIO = VREF = 3.0V. The maximum and minimum values apply for T Noise Measurement without Calibration at Gain = 1 250 230 210 190 170 150 0 200 400 600 TIME (ms) ...
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Histogram without Calibration at Gain = 8 Noise Measurement without Calibration at Gain = 128 200 400 TIME (ms) Histogram without Calibration at Gain = 128 www.national.com ...
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ENOB vs. Gain without Calibration at ODR = 13.42 SPS Noise vs. Gain without Calibration at ODR = 13.42 SPS ENOB vs. Gain without Calibration at ODR = 214.65 SPS ENOB vs. Gain with Calibration at ODR = 13.42 SPS ...
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Noise vs. Gain without Calibration at ODR = 214.65 SPS Offset Error vs. Temperature without Calibration at Gain = 1 300 250 200 150 100 50 0 -40 - TEMPERATURE (°C) Offset Error vs. ...
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Gain Error vs. Temperature without Calibration at Gain = 1 160 150 140 130 120 110 -40 - TEMPERATURE (°C) Gain Error vs. Temperature without Calibration at Gain = 8 ...
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INL at Gain = 5V, 13.4 SPS - VIN (V) www.national.com 30139527 20 ...
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Functional Description The LMP90100 is a low-power 24-Bit ΣΔ ADC with 4 fully dif- ferential or 7 single-ended analog channels. Its serial data output is two’s complement format. The output data rate (ODR) ranges from 1.6775 SPS to 214.65 ...
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The gain can be selected by programming the CHx_CONFIG: GAIN_SEL bits. 16.1.4 Buffer (BUFF) There is an internal unity gain buffer that can be included or excluded from the signal path. Including the buffer provides a high input impedance but ...
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DATA RATE ± 0.3 Hz 1.6775 SPS −109 3.355 SPS −102 6.71 SPS −100 13.42 SPS −100 26.83125 SPS 53.6625 SPS 107.325 SPS 214.65 SPS 0 -20 -40 -60 -80 -100 -120 -140 1.6775 SPS 3.355 ...
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SPS 53.6625 SPS -160 -180 0 200 FIGURE 7. Digital Filter Response, 26.83125 SPS and 53.6625 SPS 0 -20 -40 -60 -80 -100 -120 -140 107.325 SPS 214.65 SPS -160 -180 ...
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Crystal = 3.5717 MHz Crystal = 3.6864 MHz -20 -40 -60 -80 -100 -120 -140 FREQUENCY (Hz) FIGURE 9. Digital Filter Response for a 3.5717MHz versus 3.6864 MHz XTAL 16.2 CALIBRATION As seen in Figure ...
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Background Calibration Background calibration is the process of continuously deter- mining and applying the offset and gain calibration coeffi- cients to the output codes to minimize the LMP90100’s offset and gain errors. Background calibration is a feature built into ...
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System Calibration Control Register (SCALCN bits). The system zero-scale calibration must be performed prior to the full-scale calibration and both need to be repeated when the gain (or the signal ...
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LMP90100 starts a fresh conversion. 5. LMP90100 computes the system gain calibration coefficient once, stores this coefficient in the CHx_SCAL_GAIN registers, and continuously calibrates the system using this coefficient. 6. LMP90100 exits the “System Calibration Gain Coefficient Determination” mode. ...
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SENSOR INTERFACE LMP90100 contains two types of current sources: excitation currents (IB1 & IB2) and burnout currents. They are described in the next sections. 16.4.1 IB1 & IB2 - Excitation Currents IB1 and IB2 can be used for providing ...
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The sensor diagnostic flags SENDIAG_FLAGS register and are described in further de- tails below. SHORT_THLD_FLAG: The short circuit threshold flag is used to report a short-circuit condition set when the output voltage (VOUT) is within the absolute Vthreshold. ...
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SERIAL DIGITAL INTERFACE A synchronous 4-wire serial peripheral interface (SPI) pro- vides access to the internal registers of LMP90100 via CSB, SCLK, SDI, SDO/DRDYB. 16.5.1 Register Address (ADDR) All registers are memory-mapped. A register address (ADDR) is composed of ...
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SPI Protocol An SPI transaction begins when the master asserts CSB and ends when the master deasserts CSB. Each transaction must be separated by a CSB deassertion. Once CSB is asserted, it must not pulse (deassert and assert again) ...
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DrdybCase1: Combining SDO/DRDYB As shown in Figure 20, the drdyb signal and SDO can be multiplexed on the same pin as their functions are mostly complementary. In fact, this is the default mode for the SDO/DRDYB pin. Figure 21 shows ...
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DrdybCase2: Routing DRDYB to D6 The drdyb signal can be routed to pin D6 by setting SPI_DRDYB_D6 high and SDO_DRDYB_DRIVER to 0x4. This is the behavior for DrdybCase2 as shown in The timing protocol for this case can be seen ...
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Enable Data First Mode Instruction Disable Data First Mode Instruction Read Mode Status Instruction Note that while being in the data first mode, once the data bytes in the data only read transaction are sent out, the device is ready ...
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POWER MANAGEMENT The device can be placed in Active, Power-Down, or Stand- By state. In Power-Down, the ADC is not converting data, contents of the registers are unaffected, and there is a drastic power re- duction. In Stand-By, the ...
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Applications Information 17.1 QUICK START This section shows step-by-step instructions to configure the LMP90100 to perform a simple DC reading from CH0. 1. Apply VA = VIO = VREFP1 = 5V, and ground VREFN1 2. Apply VINP = ¾VREF ...
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REGISTER READ/WRITE EXAMPLES 17.4.1 Writing to Register Examples Using the register read/write protocol shown in register address (ADDR) 0x1F. CSB should pulse between each transaction, and after the last byte has been written to ADDR 0x21, deassert CSB to ...
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Reading from Register Example The following example shows how to read two bytes. The first byte will be read from starting ADDR 0x24, and the second byte will be read from ADDR 0x25. FIGURE 29. Register-Read Example 39 30139539 ...
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STREAMING EXAMPLES 17.5.1 Normal Streaming Example This example shows how to write six data bytes starting at ADDR 0x28 using the Normal Streaming mode. Because the default STRM_TYPE is the Normal Streaming mode, setting up the SPI_STREAMCN register can ...
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Controlled Streaming Example This example shows how to read the 24-bit conversion data (ADC_DOUT) four times using the Controlled Streaming mode. The ADC_DOUT registers consist of ADC_DOUTH at ADDR 0x1A, ADC_DOUTM at ADDR 0x1B, and ADC_DOUTL at ADDR 0x1C. ...
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FIGURE 32. Controlled Streaming Example 42 30139594 ...
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EXAMPLE APPLICATIONS 17.6.1 3–Wire RTD FIGURE 33. Topology #1: 3-wire RTD Using 2 Current Sources Figure 33 shows the first topology for a 3-wire resistive tem- perature detector (RTD) application. Topology #1 uses two excitation current sources, IB1 and ...
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FIGURE 34. Topology #2: 3-wire RTD Using 1 Current Source Figure 34 shows the second topology for a 3-wire RTD appli- cation. Topology #2 shows the same connection as topology #1, but without IB2. Although this topology eliminates a cur- ...
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Thermocouple and IC Analog Temperature The LMP90100 is also ideal for thermocouple temperature applications. Thermocouples have several advantages that make them popular in many industrial and medical applica- tions. Compare to RTDs, thermistors, and IC sensors, ther- mocouples are ...
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Registers 1. If written to, RESERVED bits must be written to only 0 unless otherwise indicated. 2. Read back value of RESERVED bits and registers is unspecified and should be discarded. 3. Recommended values must be programmed and forbidden ...
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Register Name CH6_CONFIG CH6 Configuration Reserved - SYSTEM CALIBRATION REGISTERS CH0_SCAL_OFFSET CH0 System Calibration Offset Coefficients CH0_SCAL_GAIN CH0 System Calibration Gain Coefficients Reserved - Reserved - CH1_SCAL_OFFSET CH1 System Calibration Offset Coefficients CH1_SCAL_GAIN CH1 System Calibration Gain Coefficient Reserved - ...
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ADC Registers ADC_RESTART: ADC Restart Conversion (Address 0x0B) Bit Bit Symbol [7:1] Reserved 0 RESTART 14.2.1. ADC_AUXCN: ADC Auxiliary Control (Address 0x12) Bit Bit Symbol 7 Reserved 6 RESET_SYSCAL 5 CLK_EXT_DET 4 CLK_SEL [3:0] RTD_CUR_SEL ADC_DONE: ...
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ADC_DOUT: 24-bit Conversion Data (two’s complement) (Address 0x1A - 0x1C) Address Name 0x1A ADC_DOUTH 0x1B ADC_DOUTM 0x1C ADC_DOUTL Note: Repeat reads of these registers are allowed as long as such reads are spaced apart by at least 72 µs. ...
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CH_SCAN: Channel Scan Mode (Address 0x1F) Bit Bit Symbol [7:6] CH_SCAN_SEL [5:3] LAST_CH [2:0] FIRST_CH Note: While writing to the CH_SCAN register, if 0x7 is written to FIRST_CH or LAST_CH the write to the entire CH_SCAN register is ignored. www.national.com ...
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CHx_INPUTCN: Channel Input Control Register Address (hex): a. CH0: 0x20 b. CH1: 0X22 c. CH2: 0x24 d. CH3: 0x26 e. CH4: 0x28 f. CH5: 0x2A g. CH6: 0x2C Bit Bit Symbol 7 BURNOUT_EN 6 VREF_SEL [5:3] VINP [2:0] VINN ...
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CHx_CONFIG: Channel Configuration Register Address (hex): a. CH0: 0x21 b. CH1: 0x23 c. CH2: 0x25 d. CH3: 0x27 e. CH4: 0x29 f. CH5: 0x2B g. CH6: 0x2D Bit Bit Symbol 7 Reserved [6:4] ODR_SEL [3:1] GAIN_SEL 0 BUF_EN www.national.com ...
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Calibration Registers BGCALCN: Background Calibration Control (Address 0x10) Bit Bit Symbol Bit Description [7:2] Reserved - Background calibration control – selects scheme for continuous background calibration. 0x0 (default): BgcalMode0: Background Calibration OFF [1:0] BGCALN 0x1: BgcalMode1: Offset ...
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Sensor Diagnostic Registers SENDIAG_THLD: Sensor Diagnostic Threshold (Address 0x14 - 0x15) Address Name 0x14 SENDIAG_THLDH 0x15 SENDIAG_THLDL SENDIAG_FLAGS: Sensor Diagnostic Flags (Address 0x19 ) Bit Bit Symbol 7 SHORT_THLD_ FLAG 6 RAILS_FLAG 5 POR_AFT_LST_RD [4:3] OFLO_FLAGS ...
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SPI Registers SPI_HANDSHAKECN: SPI Handshake Control (Address 0x01) Bit Bit Symbol Bit Description [7:4] Reserved - SDO/DRDYB Driver – sets who is driving the SDO/DRYB pin [3:1] SDO_DRDYB_ DRIVER 0x0 (default) 0x3 0x4 Others Switch-off ...
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DATA_ONLY_2: Data Only Read Control 2 (Address 0x0A) Bit Bit Symbol [7:3] Reserved [2:0] DATA_ONLY_SZ SPI_DRDYBCN: SPI Data Ready Bar Control (Address 0x11 ) Bit Bit Symbol 7 SPI_DRDYB_D6 [6:4] Reserved 5 DIS_DRDYB_QLFN 3 FGA_BGCAL [2:0] Reserved SPI_CRC_CN: CRC ...
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SPI_CRC_DAT: CRC Data (Address 0x1D ) Bit Bit Symbol Bit Description CRC Data [7:0] CRC_DAT When written, this register reset CRC: Any Value: Reset CRC When read, this register indicates the CRC data. 18.8 GPIO Registers ...
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... Physical Dimensions Order NumberLMP90100MH/NOPB, LMP90100MHE/NOPB, LMP90100MHX/NOPB www.national.com inches (millimeters) unless otherwise noted 28-Lead Molded Plastic TSSOP NS Package Number MO-153 58 ...
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Notes 59 www.national.com ...
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