HBLXT9785EHC.B2Q E000 Intel, HBLXT9785EHC.B2Q E000 Datasheet - Page 134

• Manufacturer Part Number: HBLXT9785EHC.B2Q E000
• Manufacturer: Intel

Specifications of HBLXT9785EHC.B2Q E000

• Lead Free Status / RoHS Status: Not Compliant

134
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
4.7.1
4.7.2
4.7.3
4.7.3.1
4.7.3.2
Figure 17. 100 Mbps Serial MII Data Flow
SMII Reference Clock
The REFCLK operates at 125 MHz. The transmit and receive data and control streams must always
be synchronized to the REFCLK by the MAC and PHY. The LXT9785/LXT9785E samples these
signals on the rising edge of the REFCLK.
TxSYNC Pulse (SMII/SS-SMII)
The TxSYNC pulse delimits segment boundaries and synchronizes with REFCLK. The MAC must
continuously generate a TxSYNC pulse once every 10 REFCLK cycles. The TxSYNC pulse
signals the start of each new segment
Transmit Data Stream
Transmit data and control information are signaled in ten- bit segments. In 100 Mbps mode, each
segment contains a new byte of data. In 10 Mbps mode, the MAC must repeat a 10M serial word
ten times on TxData. The LXT9785/LXT9785E may sample that serial word at any point.
The TxSYNC pulse signals the start of a new segment as shown in
Transmit Enable
The MAC must assert the TxEN bit in each segment of TxData, and de-assert TxENn after the last
segment of the packet.
Transmit Error
When the MAC asserts the TxER bit in 100BASE-X mode, the LXT9785/LXT9785E drives “H”
symbols onto the network interface. TxER does not have any function in 10M operation.
Serial Data Stream
To/From
MAC
D3 D4 D5 D6 D7
S0 S1
D0 D1 D2
TX_EN &
RX_DV
TX_ER
CRS &
Status
Status
Insert
Strip
Bits
Bits
(see Figure 21 on page
2 Nibbles Tx/Rx Data
D0 D1 D2 D3
D0 D1 D2 D3
4B/5B
139).
2 Symbols Tx/Rx Data
S0 S1 S2 S3 S4
S0 S1 S2 S3 S4
Figure
18.
Revision Date: 30-May-2006
Document Number: 249241
Revision Number: 010
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PMD
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