KSZ8041NL A3 TR Micrel Inc, KSZ8041NL A3 TR Datasheet
KSZ8041NL A3 TR
Specifications of KSZ8041NL A3 TR
Related parts for KSZ8041NL A3 TR
KSZ8041NL A3 TR Summary of contents
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... The KSZ8041NL represents a new level of features and Functional Diagram KSZ8041NL MicroLeadFrame and MLF are registered trademarks of Amkor Technology, Inc. Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 (408) 944-0800 • fax + 1 (408) 474-1000 • September 2010 KSZ8041NL/RNL 10Base-T/100Base-TX Physical Layer Transceiver Data Sheet Rev ...
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... Micrel, Inc. Features • Single-chip 10Base-T/100Base-TX physical layer solution • Fully compliant to IEEE 802.3u Standard • Low power CMOS design, power consumption of <180mW • HP auto MDI/MDI-X for reliable detection and correction for straight-through and crossover cables with disable and enable option • ...
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... Added maximum MDC clock speed. Added 40K +/-30% to note 1 of Pin Description and Strapping Options tables for internal pull-ups/pull- downs. Changed Model Number in Register 3h – PHY Identifier 2. Changed polarity (swapped definition) of DUPLEX strapping pin. Removed DUPLEX strapping pin update to Register 4h – Auto-Negotiation Advertisement bits [8, 6]. ...
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Micrel, Inc. Contents General Description .............................................................................................................................................................. 1 Functional Diagram............................................................................................................................................................... 1 Features ................................................................................................................................................................................. 2 Applications........................................................................................................................................................................... 2 Ordering Information ............................................................................................................................................................ 2 Revision History.................................................................................................................................................................... 3 List of Figures........................................................................................................................................................................ 7 List of Tables ......................................................................................................................................................................... 8 Pin Configuration – KSZ8041NL .......................................................................................................................................... 9 Pin Description – ...
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Micrel, Inc. Reduced MII (RMII) Data Interface................................................................................................................................... 25 RMII Signal Definition ....................................................................................................................................................... 26 Reference Clock (REF_CLK) ....................................................................................................................................... 26 Transmit Enable (TX_EN) ............................................................................................................................................ 26 Transmit Data [1:0] (TXD[1:0]) ..................................................................................................................................... 26 Carrier Sense/Receive Data Valid (CRS_DV).............................................................................................................. 27 Receive Data [1:0] (RXD[1:0]) ...................................................................................................................................... ...
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Micrel, Inc. Reset Circuit ........................................................................................................................................................................ 51 Reference Circuits for LED Strapping Pins...................................................................................................................... 52 Selection of Isolation Transformer.................................................................................................................................... S election of Reference Crystal .......................................................................................................................................... ackage Information........................................................................................................................................................... September 2010 6 KSZ8041NL/RNL ...
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Micrel, Inc. List of Figures Figure 1. Auto-Negotiation Flow Chart................................................................................................................................. 22 Figure 2. KSZ8041NL RMII Interface................................................................................................................................... 27 Figure 3. KSZ8041RNL RMII Interface ................................................................................................................................ 28 Figure 4. Typical Straight Cable Connection ....................................................................................................................... 29 Figure 5. Typical Crossover Cable Connection ................................................................................................................... 29 ...
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Micrel, Inc. List of Tables Table 1. MII Management Frame Format ............................................................................................................................ 23 Table 2. MII Signal Definition ............................................................................................................................................... 24 Table 3. RMII Signal Description – KSZ8041NL.................................................................................................................. 26 Table 4. RMII Signal Description – KSZ8041RNL ............................................................................................................... 26 Table 5. MDI/MDI-X ...
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Micrel, Inc. Pin Configuration – KSZ8041NL September 2010 ® 32-Pin (5mm x 5mm) MLF 9 KSZ8041NL/RNL M9999-090910-1.4 ...
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... Management Interface (MII) Clock Input This pin is synchronous to the MDIO data interface. MII Mode: Receive Data Output[3] Config Mode: The pull-up/pull-down value is latched as PHYADDR[0] during power-up / reset. See “Strapping Options” section for details. MII Mode: Receive Data Output[2] Config Mode: The pull-up/pull-down value is latched as PHYADDR[1] during power-up / reset. See “ ...
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Micrel, Inc. Pin Description – KSZ8041NL (Continued) Pin Number Pin Name Type 20 RXER / Ipd/O RX_ER / ISO 21 INTRP Opu 22 TXC 23 TXEN / TX_EN 24 TXD0 / TXD[0] 25 TXD1 / TXD[1] 26 TXD2 27 TXD3 ...
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Micrel, Inc. Pin Description – KSZ8041NL (Continued) Pin Number Pin Name Type 30 LED0 / Ipu/O NWAYEN September 2010 (1) Pin Function LED Output: Programmable LED0 Output / Config Mode: Latched as Auto-Negotiation Enable (register 0h, bit 12) during power-up ...
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... MII Tx Mode: The TXD[3..0] bits are synchronous with TXCLK. When TXEN is asserted, TXD[3..0] presents valid data from the MAC through the MII. TXD[3..0] has no effect when TXEN is de-asserted. 5. RMII Tx Mode: The TXD[1:0] bits are synchronous with REF_CLK. For each clock period in which TX_EN is asserted, two bits of data are received by the PHY from the MAC. September 2010 (1) ...
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... Pin strap-ins are latched during power-up or reset. In some systems, the MAC receive input pins may drive high during power-up or reset, and consequently cause the PHY strap-in pins on the MII/RMII signals to be latched high. In this case recommended to add 1K pull-downs on these PHY strap-in pins to ensure the PHY does not strap-in to ISOLATE mode not configured with an incorrect PHY Address. ...
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Micrel, Inc. Pin Configuration – KSZ8041RNL September 2010 ® 32-Pin (5mm x 5mm) MLF 15 KSZ8041NL/RNL M9999-090910-1.4 ...
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... I Management Interface (MII) Clock Input This pin is synchronous to the MDIO data interface. The pull-up/pull-down value is latched as PHYADDR[0] during power-up / reset. See “Strapping Options” section for details. The pull-up/pull-down value is latched as PHYADDR[1] during power-up / reset. See “Strapping Options” section for details. ...
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Micrel, Inc. Pin Description – KSZ8041RNL (Continued) Pin Number Pin Name Type 24 TXD0 25 TXD1 CONFIG0 Ipd/O 29 CONFIG1 Ipd/O 30 LED0 / Ipu/O NWAYEN September 2010 (1) Pin Function (3) I RMII Transmit ...
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... RMII Rx Mode: The RXD[1:0] bits are synchronous with REF_CLK. For each clock period in which CRS_DV is asserted, two bits of recovered data are sent from the PHY. 3. RMII Tx Mode: The TXD[1:0] bits are synchronous with REF_CLK. For each clock period in which TX_EN is asserted, two bits of data are received by the PHY from the MAC. September 2010 (1) Pin Function ...
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... Pin strap-ins are latched during power-up or reset. In some systems, the MAC receive input pins may drive high during power-up or reset, and consequently cause the PHY strap-in pins on the RMII signals to be latched high. In this case recommended to add 1K pull-downs on these PHY strap-in pins to ensure the PHY does not strap-in to ISOLATE mode not configured with an incorrect PHY Address ...
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... PHY status change. Physical signal transmission and reception are enhanced through the use of patented analog circuitries that make the design more efficient and allow for lower power consumption and smaller chip die size. ...
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Micrel, Inc. 10Base-T Receive On the receive side, input buffer and level detecting squelch circuits are employed. A differential input receiver circuit and a PLL performs the decoding function. The Manchester-encoded data stream is separated into clock signal and NRZ ...
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Micrel, Inc. Start Auto Negotiation Force Link Setting Yes Bypass Auto Negotiation and Set Link Mode September 2010 N Parallel Operation o Attempt Auto Listen for 100BASE-TX Negotiation Idles Join Flow Link Mode Set ? Yes Link Mode Set Figure ...
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... PHY devices. Each KSZ8041NL/RNL device is assigned a unique PHY address between 1 and 7 by its PHYAD[2:0] strapping pins. Also, every KSZ8041NL/RNL device supports the broadcast PHY address 0, as defined per the IEEE 802.3 Specification, which can be used to read/write to a single KSZ8041NL/RNL device, or write to multiple KSZ8041NL/RNL devices simultaneously. ...
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... Transmit Data [3:0] (TXD[3:0]) TXD[3:0] transitions synchronously with respect to TXC. When TXEN is asserted, TXD[3:0] are accepted for transmission by the PHY. TXD[3:0] is ”00” to indicate idle when TXEN is de-asserted. Values other than “00” on TXD[3:0] while TXEN is de-asserted are ignored by the PHY. ...
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... PHY. Receive Error (RXER) RXER is asserted for one or more RXC periods to indicate that a Symbol Error (e.g. a coding error that a PHY is capable of detecting, and that may otherwise be undetectable by the MAC sub-layer) was detected somewhere in the frame presently being transferred from the PHY ...
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... Transmit Data [1:0] (TXD[1:0]) TXD[1:0] transitions synchronously with respect to REF_CLK. When TX_EN is asserted, TXD[1:0] are accepted for transmission by the PHY. TXD[1:0] is ”00” to indicate idle when TX_EN is de-asserted. Values other than “00” on TXD[1:0] while TX_EN is de-asserted are ignored by the PHY. ...
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... RXD[1:0] while CRS_DV is de-asserted are ignored by the MAC. Receive Error (RX_ER) RX_ER is asserted for one or more REF_CLK periods to indicate that a Symbol Error (e.g. a coding error that a PHY is capable of detecting, and that may otherwise be undetectable by the MAC sub-layer) was detected somewhere in the frame presently being transferred from the PHY ...
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Micrel, Inc. The KSZ8041RNL RMII pin connections to the MAC are shown in Figure 3. HP Auto MDI/MDI-X HP Auto MDI/MDI-X configuration eliminates the confusion of whether to use a straight cable or a crossover cable between the KSZ8041NL/RNL and ...
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Micrel, Inc. Straight Cable A straight cable connects a MDI device to a MDI-X device MDI-X device to a MDI device. The Figure 4 depicts a typical straight cable connection between a NIC card (MDI) and a switch, ...
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Micrel, Inc. Power Management The KSZ8041NL/RNL offers the following power management modes: Power Saving Mode This mode is used to reduce power consumption when the cable is unplugged effect when auto-negotiation mode is enabled, cable is disconnected, ...
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Micrel, Inc. Reference Circuit for Power and Ground Connections The KSZ8041NL/RNL is a single 3.3V supply device with a built-in 1.8V low noise regulator. The power and ground connections are shown in Figure 8 and Table 6. Ferrite Bead 22uF ...
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... Enable auto-negotiation process Negotiation 0 = Disable auto-negotiation process Enable If enabled, auto-negotiation result overrides settings in register 0.13 and 0.8. 0.11 Power Down 1 = Power down mode 0 = Normal operation 0.10 Isolate 1 = Electrical isolation of PHY from MII and 0 = Normal operation September 2010 TX+/TX- 32 KSZ8041NL/RNL (1) Default Mode RW/ ...
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Micrel, Inc. Register Description (Continued) Address Name Description Register 0h – Basic Control 0.9 Restart Auto Restart auto-negotiation process Negotiation 0 = Normal operation. This bit is self-cleared after a ‘1’ is written to it. 0.8 Duplex Mode ...
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... PHY ID Assigned to the 3rd through 18th bits of the Number Organizationally Unique Identifier (OUI). Kendin Communication’s OUI is 0010A1 (hex) Register 3h – PHY Identifier 2 3.15:10 PHY ID Assigned to the 19th through 24th bits of the Number Organizationally Unique Identifier (OUI). Kendin Communication’s OUI is 0010A1 (hex) 3 ...
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Micrel, Inc. Register Description (Continued) Address Name Description Register 5h – Auto-Negotiation Link Partner Ability 5.15 Next Page 1 = Next page capable next page capability 5.14 Acknowledge 1 = Link code word received from partner 0 ...
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Micrel, Inc. Register Description (Continued) Address Name Description Register 7h – Auto-Negotiation Next Page 7.15 Next Page 1 = Additional next page(s) will follow 0 = Last page 7.14 Reserved 7.13 Message Page 1 = Message page 0 = Unformatted ...
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Micrel, Inc. Register Description (Continued) Address Name Description Register 1Bh – Interrupt Control/Status 1b.15 Jabber 1 = Enable Jabber Interrupt Interrupt 0 = Disable Jabber Interrupt Enable Receive Error 1b. Enable Receive Error Interrupt Interrupt 0 = Disable ...
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... State 1 = MDI-X 1e:10:8 Reserved 1e:7 Remote 0 = Normal mode loopback 1 = Remote (analog) loop back is enable 1e:6:0 Reserved Register 1Fh – PHY Control 2 1f:15 HP_MDIX 0 = Micrel Auto MDI/MDI-X mode Auto MDI/MDI-X mode 1f:14 MDI/MDI-X When Auto MDI/MDI-X is disabled, Select 0 = MDI Mode 1 = MDI-X Mode ...
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... Auto-negotiation process not completed Complete 1f.6 Enable Pause 1 = Flow control capable (Flow Control flow control capability 1f.5 PHY Isolate 1 = PHY in isolate mode 0 = PHY in normal operation 1f.4:2 Operation [000] = still in auto-negotiation Mode [001] = 10Base-T half-duplex Indication [010] = 100Base-TX half-duplex [011] = reserved [101] = 10Base-T full-duplex ...
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Micrel, Inc. Absolute Maximum Ratings Supply Voltage (V ) ............................................... -0.5V to +2.4V DDPLL_1 ................................... -0.5V to +4.0V DDIO_3.3, DDA_3.3 Input Voltage (all inputs) ............................... -0.5V to +4.0V Output Voltage (all outputs) .......................... -0.5V to +4.0V Lead ...
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... Specification for packaged product only Current consumption is for the single 3.3V supply KSZ8041NL/RNL device only, and includes the 1.8V supply voltage (V the KSZ8041NL/RNL. The PHY port’s transformer consumes an additional 45mA @ 3.3V for 100Base-TX and 70mA @ 3.3V for 10Base-T. September 2010 (4) ...
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Micrel, Inc. Timing Diagrams MII SQE Timing (10Base-T) Timing Parameter SQE t SQEP September 2010 Figure 9. MII SQE Timing (10Base-T) Description TXC period TXC pulse width low TXC pulse width high COL ...
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Micrel, Inc. MII Transmit Timing (10Base-T) Timing Parameter SU1 t SU2 t HD1 t HD2 t CRS1 t CRS2 September 2010 Figure 10. MII Transmit Timing (10Base-T) Description TXC period TXC pulse width ...
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Micrel, Inc. MII Receive Timing (10Base-T) Timing Parameter RLAT September 2010 Figure 11. MII Receive Timing (10Base-T) Description RXC period RXC pulse width low RXC pulse width high (RXD[3:0], RXER, RXDV) ...
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Micrel, Inc. MII Transmit Timing (100Base-TX) Timing Parameter SU1 t SU2 t HD1 t HD2 t CRS1 t CRS2 September 2010 Figure 12. MII Transmit Timing (100Base-TX) Description TXC period TXC pulse width ...
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Micrel, Inc. MII Receive Timing (100Base-TX) Timing Parameter RLAT September 2010 Figure 13. MII Receive Timing (100Base-TX) Description RXC period RXC pulse width low RXC pulse width high (RXD[3:0], RXER, RXDV) ...
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Micrel, Inc. RMII Timing Timing Parameter t cyc Timing Parameter t cyc September 2010 Figure 14. RMII Timing – Data Received from RMII Figure 15. RMII Timing – ...
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Micrel, Inc. Auto-Negotiation Timing Timing Parameter t BTB t FLPW CTD t CTC Table 14. Auto-Negotiation Fast Link Pulse (FLP) Timing Parameters September 2010 Figure 16. Auto-Negotiation Fast Link Pulse (FLP) Timing Description FLP Burst to FLP ...
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... MDC period P t MDIO (PHY input) setup to rising edge of MDC 1MD1 t MDIO (PHY input) hold from rising edge of MDC MD2 t MDIO (PHY output) delay from rising edge of MDC MD3 September 2010 Figure 17. MDC/MDIO Timing Table 15. MDC/MDIO Timing Parameters 49 KSZ8041NL/RNL Min Typ ...
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Micrel, Inc. Reset Timing The KSZ8041NL/RNL reset timing requirement is summarized in the following figure and table. Parameter After the de-assertion of reset recommended to wait a minimum of 100 ...
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Micrel, Inc. Reset Circuit The reset circuit in Figure 19 is recommended for powering up the KSZ8041NL/RNL if reset is triggered by the power supply. The reset circuit in Figure 20 is recommended for applications where reset is driven by ...
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Micrel, Inc. Reference Circuits for LED Strapping Pins The Figure 21 shows the reference circuits for pull-up, float and pull-down on the LED1 and LED0 strapping pins. September 2010 Pull-up KSZ8041NL/RNL LED pin Float KSZ8041NL/RNL LED pin Pull-down KSZ8041NL/RNL LED ...
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Micrel, Inc. Selection of Isolation Transformer A 1:1 isolation transformer is required at the line interface. An isolation transformer with integrated common-mode chokes is recommended for exceeding FCC requirements. The Table 17 gives recommended transformer characteristics. Parameter Turns ratio Open-circuit ...
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Micrel, Inc. Package Information MICREL, INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131 USA TEL +1 (408) 944-0800 FAX +1 (408) 474-1000 WEB The information furnished by Micrel in this data sheet is believed to be accurate and reliable. However, ...