SLXT973QCA3V 856775 Intel, SLXT973QCA3V 856775 Datasheet - Page 29
SLXT973QCA3V 856775
Manufacturer Part Number
SLXT973QCA3V 856775
Description
Manufacturer
Intel
Datasheet
1.SLXT973QCA3V_856775.pdf
(88 pages)
Specifications of SLXT973QCA3V 856775
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3.4.2.2
3.5
3.5.1
3.5.2
3.5.3
Datasheet
Document #: 249426
Revision #: 002
Rev. Date: March 1, 2002
and overall signal integrity. Regardless of clock source, careful consideration should be given to
physical placement, board layout, and signal routing of the source to maintain the highest possible
level of signal integrity. Refer to
MDIO Clock
The MII management channel (MDIO) also requires an external clock. The managed data clock
(MDC) speed is a maximum of 20 MHz. Refer to
Initialization
When the LXT973 is first powered on, reset, or encounters a link failure state, it checks the MDIO
register configuration bits to determine the line speed and operating conditions to use for the
network link. The configuration bits may be set by the Hardware Control or MDIO interface as
shown in
MDIO Control Mode
In the MDIO Control mode, the LXT973 reads the Hardware Control Interface pins to set the initial
(default) values of the MDIO registers. Once the initial values are set, bit control reverts to the
MDIO interface.
Hardware Control Mode
In the Hardware Control Mode, the LXT973 disables direct write operations to the MDIO registers
via the MDIO Interface. On power-up or hardware reset the LXT973 reads the Hardware Control
Interface pins and sets the MDIO registers accordingly.
The following modes are available using either Hardware Control or MDIO Control:
When the network link is forced to a specific configuration, the LXT973 immediately begins
operating the network interface as commanded. When auto-negotiation is enabled, the LXT973
begins the auto-negotiation/parallel-detection operation.
Power-Down Mode
The LXT973 incorporates numerous features to maintain the lowest power possible. The device
can be put into a low-power state via Register 0 as well as a near-zero power state with the power-
down pin. When in power-down mode, the device is not capable of receiving or transmitting
packets.
•
•
•
Forced network link to 100BASE-FX (Fiber)
Forced network link operation to:
100BASE-TX, full-duplex
100BASE-TX, half-duplex
10BASE-T, full-duplex
10BASE-T, half-duplex
Allow auto-negotiation/parallel-detection
Table 9 on page
LXT973 10/100 Mbps Dual-Port Fast Ethernet PHY Transceiver
31.
Table 33 on page 74
Table 49 on page 85
for clock timing requirements.
for details.
29
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