CY7B9334-270JC Cypress Semiconductor Corp, CY7B9334-270JC Datasheet - Page 11

• Manufacturer Part Number: CY7B9334-270JC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7B9334-270JC

• Lead Free Status / RoHS Status: Not Compliant

Transmitter Switching Characteristics
Receiver Switching Characteristics
Document #: 38-02014 Rev. *B
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Notes
Parameter
PPWH
PDF
RISE
FALL
DJ
RJ
RJ
CKR
B
CPRH
CPRL
RH
PRF
PRH
A
ROH
H
CKX
CPXH
CPXL
DS
SA
EFW
7. Tested initially and after any design or process changes that may affect these parameters, but not 100% tested.
8. Cypress uses constant current (ATE) load configurations and forcing functions. This figure is for reference only.
9. Transmitter t
10. Data includes D
11. t
12. Loading on RP is the standard TTL test load shown in part (a) of AC Test Loads and Waveforms except C
13. While sending continuous K28.5s, RP unloaded, outputs loaded to 50Ω to V
14. While sending continuous K28.7s, after 100,000 samples measured at the cross point of differential outputs, time referenced to CKW input, over the operating
15. The period of t
16. Receiver t
17. Data includes Q
18. t
19. REFCLK has no phase or frequency relationship with CKR and only acts as a centering reference to reduce clock synchronization time. REFCLK must be
20. The PECL switching threshold is the midpoint between the PECL− V
21. Static alignment is a measure of the alignment of the Receiver sampling point to the center of a bit. Static alignment is measured by sliding one bit edge in
22. Error Free Window is a measure of the time window between bit centers where a transition may occur without causing a bit sampling error. EFW is measured
Parameter
range.
within 0.1% of the transmitter CKW frequency, necessitating a ±500-PPM crystal.
3,000 nominal transitions until a byte error occurs.
over the operating range, input jitter < 50% Dj.
SENP
A
, t
ROH
and t
, and t
HENP
B
is calculated as t
B
H
Read Clock Period (No Serial Data Input), REFCLK as Reference
Bit Time
Read Clock Pulse HIGH
Read Clock Pulse LOW
RDY Hold Time
RDY Pulse Fall to CKR Rise
RDY Pulse Width HIGH
Data Access Time
Data Hold Time
Data Hold Time from CKR Rise
REFCLK Clock Period Referenced to CKW of Transmitter
REFCLK Clock Pulse HIGH
REFCLK Clock Pulse LOW
Propagation Delay SI to SO (note PECL and TTL thresholds)
Static Alignment
Error Free Window
CKR
is calculated as t
specifications are only valid if all outputs (CKR, RDY, Q
timing insures correct RP function and correct data load on the rising edge of CKW.
0−7
0−7
will match the period of the transmitter CKW when the receiver is receiving serial data. When data is interrupted, CKR may drift to one of the range limits above.
, SC/D, SVS, ENA, ENN, and BISTEN. t
, SC/D, and RVS.
Read Pulse HIGH
Read Pulse Fall Alignment
PECL Output Rise Time 20−80% (PECL Test Load)
PECL Output Fall Time 80−20% (PECL Test Load)
Deterministic Jitter (peak-peak)
Random Jitter (peak-peak)
Random Jitter (σ)
[16]
CKR
CKW
/10 if no data is being received, or t
[17, 18]
/10. The byte rate is one tenth of the bit rate.
[7, 21]
[17, 18]
[7, 22]
[7,14]
[12]
Description
Description
[12]
[7, 14]
[17, 18]
SD
and t
[7, 13]
Over the Operating Range
CKW
HD
0−7
Over the Operating Range
minimum timing assures correct data load on rising edge of CKW, but not RP function or timing.
/10 if data is being received. See note.
, SC/D, and RVS) are loaded with similar DC and AC loads.
OH
, and V
CC
−2.0V, over the operating range.
OL
specification (approximately V
[7]
[7]
[19]
[1]
[20]
[1]
[15]
L
= 15 pF.
(continued)
4t
6t
t
t
5t
5t
5t
4t
2t
2t
7B9234-270
0.9t
B
B
Min
−0.1
Min
3.03
7B9334-270
6.5
6.5
−1
−2.5
−2.5
B
B
B
B
B
B
B
B
−3
−3
−3
−3
−3
−3
−2
−3
CC
B
− 1.35V). The TTL switching threshold is 1.5V.
2t
Max
+0.1
Max
175
6.25
100
1.2
1.2
35
20
+1
20
B
+4
4t
6t
t
t
7B9234-400
5t
5t
5t
4t
2t
2t
0.9t
Min
B
B
−0.1
Min
7B9334-400
2.5
6.5
6.5
−1
B
B
−2.5
−2.5
B
B
B
B
B
B
−3
−3
−3
−3
−3
−3
−2
−3
B
Max
175
2t
1.2
1.2
+0.1
Max
6.25
35
20
CY7B9234
CY7B9334
100
+1
20
B
+4
Page 11 of 36
Unit
Unit
ns
ns
ns
ns
ps
ps
ps
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ps
%
%
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