CY7B933-JC Cypress Semiconductor Corp, CY7B933-JC Datasheet - Page 15

• Manufacturer Part Number: CY7B933-JC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7B933-JC

• Lead Free Status / RoHS Status: Not Compliant

BIST Mode
The BIST mode functions as follows:
Document #: 38-02017 Rev. *H
1. Set BISTEN LOW to begin test pattern generation. The trans-
2. Set either ENA or ENN LOW to begin pattern sequence
3. Allow the transmitter to run through several BIST loops or until
mitter begins sending bit rate ...1010...
generation (use of the Enable pin not being used for normal
FIFO or system interface can minimize logic delays between
the controller and transmitter).
the receiver test is complete. RP will pulse LOW once per
START
Tx
BEGIN
TEST
Rx
ERROR
START
TEST
LOOP
BIST
LOOP
BIST
TEST
END
Figure 8. BIST Illustration
STOP
WITHIN SPEC.
WITHIN SPEC.
Tx
DON'T CARE
DON'T CARE
DON'T CARE
DON'T CARE
DON'T CARE
HIGH
LOW
LOW
8
8
Note: It may be advisable to send violation characters to test the
RVS output in the receiver. This can be done by explicitly
sending a violation with the SVS input, or allowing the transmitter
BIST loop to run while the receiver runs in normal mode. The
BIST loop includes deliberate violation symbols and will
adequately test the RVS function.
4. When testing is completed, set BISTEN HIGH and ENA and
BIST loop, and can be used by an external counter to monitor
the number of test pattern loops.
ENN HIGH and resume normal function.
FOTO
MODE
CKW
RP
SC/D
D
SVS
ENA
ENN
BISTEN
REFCLK
MODE
RF
CKR
SC/D
Q
RVS
RDY
BISTEN
0–7
0–7
CY7B923
CY7B933
CY7B923, CY7B933
OUTC
OUTA
OUTB
INA
INB
A/B
SO
DON'T CARE
LOW
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