DP83848MSQ National Semiconductor, DP83848MSQ Datasheet - Page 18

• Manufacturer Part Number: DP83848MSQ
• Manufacturer: National Semiconductor

Specifications of DP83848MSQ

• Lead Free Status / RoHS Status: Compliant

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2.4 LED Interface
The DP83848M supports a configurable Light Emitting
Diode (LED) pin for configuring the link. The PHY Control
Register (PHYCR) for the LED can also be selected
through address 19h, bit [5].
See Table 3 for LED Mode selection.
The LED_LINK pin in Mode 1 indicates the link status of
the port. In 100BASE-T mode, link is established as a
result of input receive amplitude compliant with the TP-
PMD specifications which will result in internal generation
of signal detect. A 10 Mb/s Link is established as a result
of the reception of at least seven consecutive normal Link
Pulses or the reception of a valid 10BASE-T packet. This
will cause the assertion of LED_LINK. LED_LINK will
deassert in accordance with the Link Loss Timer as speci-
fied in the IEEE 802.3 specification.
The LED_LINK pin in Mode 1 will be OFF when no LINK is
present.
The LED_LINK pin in Mode 2 will be ON to indicate Link is
good and BLINK to indicate activity is present on either
transmit or receive activity.
Since the LED_LINK pin is also used as a strap option,
the polarity of the LED is dependent on whether the pin is
pulled up or down.
2.4.1 LED
Since the Auto-Negotiation (AN0) strap option shares the
LED_LINK output pin, the external components required
for strapping and LED usage must be considered in order
to avoid contention.
Specifically, when the LED output is used to drive the LED
directly, the active state of the output driver is dependent
on the logic level sampled by the AN0 input upon power-
up/reset. For example, if the AN0 input is resistively pulled
low then the corresponding output will be configured as an
active high driver. Conversely, if the AN0 input is resis-
tively pulled high, then the corresponding output will be
configured as an active low driver.
Refer to Figure 3 for an example of AN0 connection to
external components. In this example, the AN0 strapping
results in Auto-Negotiation with 10/100 Half/Full-Duplex
advertised.
The adaptive nature of the LED output helps to simplify
potential implementation issues of this dual purpose pin.
Mode
1
2
(bit 5) or (pin33)
Table 3. LED Mode Select
LED_CFG[0]
1
0
ON for Good Link
OFF for No Link
ON for Good Link
BLINK for Activity
LED_LINK
18
2.4.2 LED Direct Control
The DP83848M provides another option to directly control
the LED output through the LED Direct Control Register
(LEDCR), address 18h. The register does not provide
read access to the LED.
Figure 3. AN0 Strapping and LED Loading Example
VCC