CY7C9689A-AI Cypress Semiconductor Corp, CY7C9689A-AI Datasheet - Page 19

• Manufacturer Part Number: CY7C9689A-AI
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C9689A-AI

• Lead Free Status / RoHS Status: Not Compliant

Document #: 38-02020 Rev. *D
If a large number of errors are detected, the receive BIST state
machine aborts the compare operations and resets the LFSR
to the D0.0 state to look for the start of the BIST sequence
again.
Receive Control State Machine
The Receive Control State Machine responds to multiple input
conditions to control the routing and handling of received
characters. It controls the staging of characters across various
registers and the Receive FIFO. It controls the various discard
policies and error control within the receiver, and operates in
response to:
These signals and conditions are used by the Receive Control
State Machine to control the Receive Formatter, write access
to the Receive FIFO, the Receive Output register, and BIST.
They determine the content of the characters passed to each
of these destinations.
The Receive Control State Machine always operates
synchronous to the recovered character clock (bit-clock/10 or
bit-clock/12). When the Receive FIFO is bypassed, RXCLK
becomes an output that changes synchronous to the internal
character clock. RXCLK operates at the same frequency as
the internal character clock.
Discard Policies
When the Receive FIFO is enabled, the Receive Control State
Machine has the ability to selectively discard specific
characters from the data stream that are determined by the
present configuration as being unnecessary. When discarding
is enabled, it reduces the host system overhead necessary to
keep the Receive FIFO from overflowing and losing data.
The discard policy is configured as part of the operating mode
and is set using the RXMODE[1:0] inputs. The four discard
policies are listed in
Policy 0 is the simplest and also applies for all conditions
where the Receive FIFO is bypassed. In this mode, every
character that is received is placed into the Receive FIFO
(when enabled) or into the Receive Output Register.
In discard policy 1, the JK or LM SYNC character, which is
automatically transmitted when no data is present in the
Transmit FIFO, is treated differently here. In this mode,
whenever two or more adjacent JK or LM characters are
received, all of them are discarded except the last one
received before any other character type. This allows these fill
characters to be removed from the data stream, but the last
SYNC character which can be used as a delimiter.
Policy 2 is identical to policy 1 except that all C5.0 characters
are removed from the data stream.
When the FIFOs are bypassed (FIFOBYP LOW), no
characters are actually discarded, but the receiver discard
policy can be used to control external filtering of the data. The
RXEMPTY FIFO flag is used to indicate if the character on the
output bus is valid or not. In discard policy 0, the RXEMPTY
flag is always deasserted to indicate that valid data is always
•the received character stream
•the room for additional data in the Receive FIFO
•the state of the receiver BIST enable (RXBISTEN)
•the state of FIFOBYP.
Table
5.
present. In discard policy 1, the RXEMPTY flag indicates an
empty condition for all but the last JK or LM character before
any other character is presented. In discard policy 2, the
RXEMPTY flag indicates an empty condition for all JK or LM
SYNC characters. When any other character is present, this
flag indicates that valid or “interesting” Data or Special
Characters are present.
Receive FIFO
The Receive FIFO is used to buffer data captured from the
selected serial stream for later processing by the host system.
This FIFO is sized to hold 256 14-bit characters. When the
FIFO is enabled, it is written to by the Receive Control State
Machine. When data is present in the Receive FIFO (as
indicated by the RXFULL, RXHALF, and RXEMPTY Receive
FIFO status flags), it can be read from the Output Register by
asserting CE and RXEN.
The read port on the Receive FIFO may be configured for the
same two timing models as the transmit interface: UTOPIA
and Cascade. Both are forms of a FIFO interface. The UTOPIA
timing model has active LOW RXEMPTY and RXFULL status
flags, and an active LOW RXEN enable. When configured for
Cascade operation, these same signals are all active HIGH.
Either timing model supports connection to various host bus
interfaces, state machines, or external FIFOs for depth
expansion (see Figure 4)
The Receive FIFO presents Full, Half-Full, and Empty FIFO
status flags. These flags are provided synchronous to RXCLK
to allow operation with a Moore-type external controlling state
machine. When configured with the Receive FIFO enabled,
RXCLK is an input. When the Receive FIFO is bypassed
(FIFOBYP is LOW), RXCLK is an output operating at the
received character rate.
Receive Input Register
The input register is clocked by the rising edge of RXCLK. It
samples numerous signals that control the reading of the
EF*
REN*
Q
RXCLK
Figure 4. External FIFO Depth Expansion of the
CY7C9689A Receive Data Path)
CY7C42x5 FIFO
RCLK
EF*
REN*
Q
WCLK
WEN*
FF*
D
“1”
CY7C9689A
CY7C9689A
EXTFIFO
RXEN
RXEMPTY
RXCLK
RXDATA
RXSC/D
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