KSZ8041NL Micrel Inc, KSZ8041NL Datasheet - Page 13

no-image

KSZ8041NL

Manufacturer Part Number
KSZ8041NL
Description
Manufacturer
Micrel Inc
Datasheet

Specifications of KSZ8041NL

Lead Free Status / RoHS Status
Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
KSZ8041NL
Manufacturer:
MICREL
Quantity:
700
Part Number:
KSZ8041NL
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
Company:
Part Number:
KSZ8041NL
Quantity:
839
Company:
Part Number:
KSZ8041NL
Quantity:
73
Part Number:
KSZ8041NL AM
Manufacturer:
Micrel Inc
Quantity:
1 997
Part Number:
KSZ8041NL TR
Manufacturer:
Kendin
Quantity:
247 880
Part Number:
KSZ8041NL TR
Manufacturer:
FUJI
Quantity:
272
Part Number:
KSZ8041NL TR
Manufacturer:
MICREL
Quantity:
1 000
Part Number:
KSZ8041NL TR
Manufacturer:
MICREL/麦瑞
Quantity:
20 000
Company:
Part Number:
KSZ8041NL TR
Quantity:
537
Part Number:
KSZ8041NL-AM-TR
0
Part Number:
KSZ8041NL-TR
Manufacturer:
MICREL
Quantity:
20 000
Part Number:
KSZ8041NL-TR
0
Part Number:
KSZ8041NLA4TR
Manufacturer:
MICREL/麦瑞
Quantity:
20 000
Part Number:
KSZ8041NLI
Manufacturer:
MELEXIS
Quantity:
827
Part Number:
KSZ8041NLI
Manufacturer:
MICREL/麦瑞
Quantity:
20 000
Part Number:
KSZ8041NLI-TR
0
Micrel, Inc.
Pin Description – KSZ8041NL (Continued)
September 2010
Pin Number
31
32
PADDLE
Notes:
1. P = Power supply.
2. MII Rx Mode: The RXD[3..0] bits are synchronous with RXCLK. When RXDV is asserted, RXD[3..0] presents valid data to MAC through the
3. RMII Rx Mode: The RXD[1:0] bits are synchronous with REF_CLK. For each clock period in which CRS_DV is asserted, two bits of
4. MII Tx Mode: The TXD[3..0] bits are synchronous with TXCLK. When TXEN is asserted, TXD[3..0] presents valid data from the MAC through
5. RMII Tx Mode: The TXD[1:0] bits are synchronous with REF_CLK. For each clock period in which TX_EN is asserted, two bits of data are
Gnd = Ground.
I = Input.
O = Output.
I/O = Bi-directional.
Ipd = Input with internal pull-down (40K +/-30%).
Ipu = Input with internal pull-up (40K +/-30%).
Opu = Output with internal pull-up (40K +/-30%).
Ipu/O = Input with internal pull-up (40K +/-30%) during power-up/reset; output pin otherwise.
Ipd/O = Input with internal pull-down (40K +/-30%) during power-up/reset; output pin otherwise.
MII. RXD[3..0] is invalid when RXDV is de-asserted.
recovered data are sent from the PHY.
the MII. TXD[3..0] has no effect when TXEN is de-asserted.
received by the PHY from the MAC.
Pin Name
LED1 /
SPEED
RST#
GND
Ipu/O
I
Gnd
Type
(1)
Pin Function
LED Output:
Config Mode:
The LED1 pin is programmable via register 1Eh bits [15:14], and is defined as
follows.
LED mode = [10]
Reserved
LED mode = [11]
Reserved
Chip Reset (active low)
Ground
LED mode = [00]
Speed
10BT
100BT
LED mode = [01]
Activity
No Activity
Activity
Programmable LED1 Output /
Latched as SPEED (register 0h, bit 13) during power-up / reset.
See “Strapping Options” section for details.
Pin State
Toggle
Pin State
H
L
H
13
LED Definition
OFF
ON
LED Definition
Blinking
OFF
M9999-090910-1.4
KSZ8041NL/RNL

Related parts for KSZ8041NL