SLXT973QCA3V Cortina Systems Inc, SLXT973QCA3V Datasheet - Page 18
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SLXT973QCA3V
Manufacturer Part Number
SLXT973QCA3V
Description
Manufacturer
Cortina Systems Inc
Datasheet
1.SLXT973QCA3V.pdf
(88 pages)
Specifications of SLXT973QCA3V
Lead Free Status / RoHS Status
Not Compliant
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Part Number
Manufacturer
Quantity
Price
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Part Number:
SLXT973QCA3V
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LXT973 10/100 Mbps Dual-Port Fast Ethernet PHY Transceiver
18
Table 3.
Table 4.
LXT973 Port 1 Signal Descriptions (Continued)
LXT973 Network Interface Signal Descriptions
3
4
19
22
23
1. AI = Analog Input, AO = Analog Output, I = Input, O = Output, OD = Open Drain output,
Pin #
1. AI = Analog Input, AO = Analog Output, I = Input, O = Output, OD = Open Drain output,
Pin #
59
60
63
64
76
ST = Schmitt Triggered input, TS = Tri-State-able output, SL = Slew-rate Limited output,
IP = Weak Internal Pull-up, ID = Weak Internal Pull-Down
ST = Schmitt Triggered input, TS = Tri-State-able output, SL = Slew-rate Limited output,
IP = Weak Internal Pull-up, ID = Weak Internal Pull-Down
DPBN_0
DPAP_0
DPAN_0
DPBP_0
Names
Signal
COL1
CRS1
MDDIS1
MDC1
MDIO1
Signal Names
SD0
RX+
TX+
RX-
TX-
Op
TP
-
Type
O, TS
O, TS
Fiber
RX+
TX+
RX-
TX-
Op
I/O
-
I
I
1
Port
Collision Detected. The LXT973 asserts this output when a collision
is detected. This output remains High for the duration of the collision.
COL is asynchronous and is inactive during full-duplex operation.
Carrier Sense. During half-duplex operation, the LXT973 asserts this
output when either the transmit or receive medium is non-idle. During
full-duplex operation, CRS1 is asserted only when receive medium is
non-idle.
Management Disable. When MDDIS is tied High, the MDIO port is
completely disabled and the Hardware Control Interface pins set their
respective bits at power-up and reset.
When MDDIS is pulled Low at power-up or reset via the internal pull-
down resistor or by tieing it to ground, the Hardware Control Interface
Pins control only the initial or “default” values of their respective
register bits. After the power-up/reset cycle is complete, bit control
reverts to the MDIO serial channel.
Management Data Clock. Clock for MDIO1 serial channel. Maximum
frequency is 20 MHz.
(Note:
of product.)
Management Data Input/Output. Bidirectional serial data channel for
PHY/STA communication.
0
0
0
0
-
Type
Pair
20 MHz value to be verified prior to final production release
A
A
B
B
-
AI/AO,
AI/AO,
Type
SL
SL
I
1
Twisted-Pair/Fiber Pair A, Positive &
Negative - Port 0. Differential pair produces
or receives IEEE 802.3-compliant pulses for
either 100BASE-TX or 10BASE-T.
Also acts as receiver in Fiber mode.
Twisted-Pair/Fiber Pair B, Positive &
Negative - Port 0. Differential pair produces
or receives IEEE 802.3-compliant pulses for
either 100BASE-TX or 10BASE-T.
Also acts as transmitter in Fiber mode.
Signal Detect. This signal is used for signal
quality indication in Fiber mode. In twisted-
pair mode, this pin should be tied Low.
Signal Description
Signal Description
Rev. Date: March 1, 2002
Document #: 249426
Revision #: 002
Datasheet