DJLXT971ALE.A4 Cortina Systems Inc, DJLXT971ALE.A4 Datasheet - Page 58
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DJLXT971ALE.A4
Manufacturer Part Number
DJLXT971ALE.A4
Description
Manufacturer
Cortina Systems Inc
Datasheet
1.DJLXT971ALE.A4.pdf
(96 pages)
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LXT971A PHY
Datasheet
249414, Revision 5.2
13 September 2007
Figure 25
Cortina Systems
Typical Interface - LXT971A PHY to 3.3 V Fiber PHY
The following occurs in 5 V fiber PHY applications as shown in
Figure 26
fiber PHY.
®
• The transmit pair should be AC-coupled and re-biased to 5 V PECL input levels.
• The transmit pair should contain a balance offset in the bias resistors to prevent PHY-
• The receive pair should be AC-coupled with an emitter current path for the fiber PHY
• The signal detect pin on a 5 V fiber PHY interface should use the logic translator
LXT971A Single-Port 10/100 Mbps PHY Transceiver
to-fiber PHY crosstalk amplification in power-down, loopback, and reset states. (See
the fiber interface application note.)
and re-biased to 3.3 V LVPECL input levels.
circuitry as shown in
1. Refer to the manufacturers’ recommendations for termination circuitry.
LXT97x PHY
shows a typical example of an interface between the LXT971A PHY and a 5 V
SD/TP_L
TPFON
TPFOP
TPFIN
TPFIP
Figure
+3.3 V
0.01 μF −
16 Ω
0.1 μF
2.74 kΩ
50 Ω
+3.3 V
+3.3 V
26.
0.01 μF - 0.1 μF
50 Ω
130 Ω
82 Ω
130 Ω
82 Ω
+3.3 V
130 Ω
82 Ω
TD +
Figure
TD -
Fiber Txcvr
RD -
RD +
SD
3.3 V
1
B3402-02
26:
6.3 Fiber Interface
Page 58
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