WJLXT971ALE.A4-857346 Cortina Systems Inc, WJLXT971ALE.A4-857346 Datasheet - Page 18

• Manufacturer Part Number: WJLXT971ALE.A4-857346
• Manufacturer: Cortina Systems Inc

Specifications of WJLXT971ALE.A4-857346

• Lead Free Status / RoHS Status: Compliant

LXT971A PHY
Datasheet
249414, Revision 5.2
13 September 2007
Table 5
Cortina Systems
MII Data Interface Signal Descriptions
®
PBGA
Pin#
LXT971A Single-Port 10/100 Mbps PHY Transceiver
A3
B3
C4
A4
B4
C5
D6
C8
B8
A8
A7
A5
B5
B6
B2
A2
LQFP
Pin#
60
59
58
57
56
55
45
46
47
48
49
53
54
52
62
63
TX_CLK
RX_CLK
Symbol
RX_DV
RX_ER
TX_EN
TX_ER
TXD3
TXD2
TXD1
TXD0
RXD3
RXD2
RXD1
RXD0
CRS
COL
Type
O
O
O
O
O
O
O
I
I
I
Transmit Data.
TXD is a group of parallel data signals that are driven by the MAC.
TXD[3:0] transition synchronously with respect to TX_CLK.
TXD[0] is the least-significant bit.
Transmit Enable.
The MAC asserts this signal when it drives valid data on TXD.
This signal must be synchronized to TX_CLK.
Transmit Clock.
TX_CLK is sourced by the PHY in both 10 and 100 Mbps
operations.
2.5 MHz for 10 Mbps operation
25 MHz for 100 Mbps operation.
Receive Data.
RXD is a group of parallel signals that transition synchronously with
respect to RX_CLK.
RXD[0] is the least-significant bit.
Receive Data Valid.
The PHY asserts this signal when it drives valid data on RXD.
This output is synchronous to RX_CLK.
Receive Error.
Signals a receive error condition has occurred.
This output is synchronous to RX_CLK.
Transmit Error.
Signals a transmit error condition.
This signal must be synchronized to TX_CLK.
Receive Clock.
25 MHz for 100 Mbps operation.
2.5 MHz for 10 Mbps operation.
For details, see
the Functional Description section.
Collision Detected.
The PHY asserts this output when a collision is detected.
This output remains High for the duration of the collision.
This signal is asynchronous and is inactive during full- duplex
operation.
Carrier Sense.
During half-duplex operation (register bit 0.8 = 0), the PHY asserts
this output when either transmitting or receiving data packets.
During full-duplex operation (register bit 0.8 = 1), CRS is asserted
only during receive.
CRS assertion is asynchronous with respect to RX_CLK. CRS is
de-asserted on loss of carrier, synchronous to RX_CLK.
Section 5.3.2, Clock Requirements, on page 30
Signal Description
4.0 Signal Descriptions
Page 18
in