MC145745FW Freescale, MC145745FW Datasheet - Page 3

• Manufacturer Part Number: MC145745FW
• Manufacturer: Freescale

Specifications of MC145745FW

• Main Category: Single Chip
• Power Supply Type: Analog
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.5V
• Operating Temperature Classification: Commercial
• Pin Count: 28
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Supplier Unconfirmed

MOTOROLA
PIN DESCRIPTIONS
16, 17, 18
16, 17, 18
Location
15, 28
1, 14
5, 24
Pin
10
12
13
19
20
21
22
23
11
2
3
4
6
7
8
9
PB1, PB2,
PB1, PB2,
SCPCLK
Symbol
TEST 1,
SCP Tx
SCP Rx
SCPEN
TEST 2
RESET
CLKO
ECLK
GND
CDA
V CC
RxD
PB0
PB3
PB3
V ref
TLA
TxD
CD
X1
X2
Type
I/O
—
—
—
—
—
O
O
O
O
O
O
O
O
I
I
I
I
I
I
I
Ground — These are the ground pins of the digital and the analog circuits. The 0 V potential of the
device is determined by the input voltage at these pins.
Reference Analog Ground — This pin provides the analog ground voltage V CC /2, which is regulated
internally. This pin should be decoupled to GND with 0.1 F and 100 F capacitors.
Carrier Detect Level Adjustment — The detection level for FSK/call–progress tone is determined
according to the voltage at this pin. When V CC = 5 V and the carrier detection level bit (BR3:b1) of the
SCP register is 0, or when V CC = 3.6 V and (BR3:b1) is 1, the CDA voltage is set to 1.25 V by the
internal divider.
This voltage sets the detection levels at ON to OFF: – 44 dBm (typ) and OFF to ON: – 47 dBm (typ).
This high impedance pin should be decoupled to GND with a 0.1 F capacitor.
The carrier detection level is proportional to the terminal voltage at this pin.
An external voltage may be applied to this pin to adjust the carrier detect threshold. The following
equations may be used to find the CDA voltage requirements for a given threshold voltage.
Transmit Level Adjustment — This pin is used to adjust the transmit carrier level which is determined
by the resistor (RTLA) connected between this pin and GND. The maximum level is obtained when
this pin is shorted to GND (RTLA = 0).
Test Pins 1 and 2 — These test pins are for manufacturer’s use only. These pins should be left open in
normal operation.
Receive Data Output — This pin is the receive data output. When the device is in the FSK mode, logic
high on this pin indicates that the mark carrier frequency has been received from RxA, and the logic
low indicates that the space carrier frequency has been received.
Transmit Data Input — This pin is the transmit data input. When the device is in the FSK mode, logic
high on this pin generates the mark frequency at TxA1 and TxA2 output, and logic low generates the
space frequency.
Carrier Detect Output — This pin outputs at low level if a valid FSK, DTMF, or CPTD signal is
received. If the pin is at high level, the receive data output pin (RxD) is internally clamped at high level
to avoid erroneous output of received data caused by line noise.
Clock Output — This pin provides a buffered 3.58 MHz clock output that can drive one CMOS device
such as the MC74HC04.
Crystal Oscillator Circuit Output — A 3.579545 MHz
other end connected to X2.
Crystal Oscillator Circuit Input — A 3.579545 MHz
other end connected to X1. X2 may be driven directly from an appropriate external clock source.
External Clock Input — ECLK is the input of double frequency, 7.159090 MHz
clock. This pin must be connected to GND when not in use.
DTMF Receive Data Parallel Output 0 (LSB) — Pins 13, 16, 17, and 18 are the DTMF receive data
parallel output occurring together with the CD (Pin 8) data valid output. The outputs of these pins are
valid as long as the CD pin is low. In power down modes 1 and 2, the DTMF receiver is disabled and
these pins are in high impedance.
Positive Power Supply — These are the power supply pins for the digital and the analog circuits.
These pins should be decoupled to GND with 0.1 F and 100 F capacitors.
DTMF Receive Data Parallel Outputs 1, 2, and 3 (MSB) — These pins are the DTMF receiver data
DTMF Receive Data Parallel Outputs 1, 2, and 3 (MSB) — These pins are the DTMF receiver data
parallel outputs See pin 13 for more details
parallel outputs. See pin 13 for more details.
Reset — A high to low trigger pulse applied to this pin sets all the registers in the default state. It
should remain at high during normal operations.
SCP Output Transmit — Refer to Serial Control Port (SCP Interface) for additional information.
SCP Receive Input — Refer to Serial Control Port (SCP Interface) for additional information.
SCP Clock — Refer to Serial Control Port (SCP Interface) for additional information.
SCP Enable — Refer to Serial Control Port (SCP Interface) for additional information.
V CDA = 256 x V on
V CDA = 362 x V off
Description
0.1% crystal oscillator is tied to this pin with the
0.1% crystal oscillator is tied to this pin with the
0.1%, of the reference
MC145745
3