ADV7611BSWZ-P-RL Analog Devices Inc, ADV7611BSWZ-P-RL Datasheet - Page 5

• Manufacturer Part Number: ADV7611BSWZ-P-RL
• Description: 1 INPUT LOW POWER STAND ALONE HDMI 1.4RX
• Manufacturer: Analog Devices Inc

Specifications of ADV7611BSWZ-P-RL

• Number Of Transmitters: Not Required
• Power Supply Requirement: Single
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 64
• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Dual Supply Voltage (typ): Not RequiredV
• Dual Supply Voltage (max): Not RequiredV
• Dual Supply Voltage (min): Not RequiredV
• Lead Free Status / RoHS Status: Compliant

DATA AND I
Table 2.
Parameter
CLOCK AND CRYSTAL
I
RESET FEATURE
CLOCK OUTPUTS
DATA AND CONTROL OUTPUTS
I
TDM SERIAL TIMING
1
2
3
4
5
6
2
2
Maximum LLC frequency is limited by the clock frequency of UXGA 60 Hz at 8 bit.
Data guaranteed by characterization.
With the DLL block on output clock bypassed.
DLL bypassed on clock path.
I
I
C PORTS
S PORT, MASTER MODE
2
2
S is accessible via the AP pin.
S_TDM is accessible via the AP pin.
Crystal Frequency, XTALP
Crystal Frequency Stability
LLC Frequency Range
SCL Frequency
SCL Minimum Pulse Width High
SCL Minimum Pulse Width Low
Start Condition Hold Time
Start Condition Setup Time
SDA Setup Time
SCL and SDA Rise Time
SCL and SDA Fall Time
Stop Condition Setup Time
Reset Pulse Width
LLC Mark-Space Ratio
Data Output Transition Time
SCLK Mark-Space Ratio
LRCLK Data Transition Time
LRCLK Data Transition Time
I
I
SCLK Mark-Space Ratio
LRCLK Data Transition Time
LRCLK Data Transition Time
I
I
2
2
2
2
S Data Transition Time
S Data Transition Time
S_TDM Data Transition Time
S_TDM Data Transition Time
2
C TIMING CHARACTERISTICS
2
6
1
2
2
2
2
2
5,
5
,
2
2
2
2
2
2
2
2
2
2
3
, 4
2
2
,
,
2
3
3
2
Symbol
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
1
2
3
4
5
6
7
8
9
11
12
15
17
18
19
20
21
23
24
25
26
:t
:t
:t
10
16
22
Test Conditions/Comments
End of valid data to negative clock edge
Negative clock edge to start of valid data
End of valid data to negative SCLK edge
Negative SCLK edge to start of valid data
End of valid data to negative SCLK edge
Negative SCLK edge to start of valid data
End of valid data to negative SCLK edge
Negative SCLK edge to start of valid data
End of valid data to negative SCLK edge
Negative SCLK edge to start of valid data
Rev. 0 | Page 5 of 16
Min
13.5
600
1.3
600
600
100
0.6
5
45:55
45:55
45:55
Typ
28.63636
1.0
0.0
Max
±50
165
400
300
300
55:45
2.2
0.3
55:45
10
10
5
5
55:45
10
10
5
5
ADV7611
Unit
MHz
ppm
MHz
kHz
ns
µs
ns
ns
ns
ns
ns
µs
ms
% duty
cycle
ns
ns
% duty
cycle
ns
ns
ns
ns
% duty
cycle
ns
ns
ns
ns