LU82562GZ Intel, LU82562GZ Datasheet
LU82562GZ
Specifications of LU82562GZ
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LU82562GZ Summary of contents
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... In addition, this device has been tested and conforms to the same parametric specifications as previous versions of the device. For more information regarding lead-free products from Intel Corporation, contact your Intel Field Sales repre- sentative. Additional Features The 82562GZ PLC supports drop-in replacement with the 82562EZ not used as a drop-in replacement, strapping options enable new operating modes: — ...
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... Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800- 548-4725 or by visiting Intel's website at http://www.intel.com. ...
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Contents 1.0 Introduction ...................................................................................................................... 1 1.1 Overview ............................................................................................................... 1 1.2 References ............................................................................................................ 1 1.3 Product Codes....................................................................................................... 1 2.0 82562GZ Architectural Overview ....................................................................................3 2.1 LAN Connect Interface .......................................................................................... 3 2.1.1 Reset/Synchronize Operations.................................................................4 2.1.2 Reset Considerations ............................................................................... 4 2.1.3 LAN Connect Clock ...
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Networking Silicon 5.4 Dynamic Reduced Power & Auto Plugging Detection......................................... 17 5.4.1 Auto Plugging Detection......................................................................... 18 5.4.2 Dynamic Reduced Power....................................................................... 18 5.4.3 Configuration.......................................................................................... 18 6.0 Platform LAN Connect Registers ................................................................................. 19 6.1 Medium Dependent Interface Registers 0 through ...
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Voltage and Temperature Specifications.....................................................................31 8.1 Absolute Maximum Ratings.................................................................................31 8.2 DC Characteristics .............................................................................................31 8.2.1 X1 Clock DC Specifications ...................................................................31 8.2.2 LAN Connect Interface DC Specifications .............................................32 8.2.3 LED DC Specifications ..........................................................................32 8.2.4 10BASE-T Voltage and Current DC Specifications ...............................32 8.2.5 ...
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... Programming information can be obtained through your local Intel representatives. 1.3 Product Codes The product ordering code for the 82562GZ is: GD82562GZ. The product ordering code for the 82562GZ lead-free version is: LU82562GZ. Datasheet Networking Silicon — 82562GZ ® 82562GZ 10/100 Mbps Platform LAN Connect (PLC) ...
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... The 82562GZ PLC is a 3.3 V device in a 196-pin Ball Grid Array (BGA) that is designed to work only in Data Terminal Equipment (DTE) mode. In normal operating mode, the 82562GZ incorporates all active circuitry required to interface with the Intel 10/100 Mbps LAN controller. The 82562GZ supports a direct interface to all Media Access Control (MAC) components that meet the Platform LAN connect interface specification ...
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Networking Silicon I/O Control Hub I/O Control Hub 4 LAN Controller (ICH4) LAN Controller System Bus Interface Figure 2. 82562GZ PLC 10/100 Mbps Ethernet Solution 2.1.1 Reset/Synchronize Operations The Reset/Synchronize signal used by the LAN Connect Interface is ...
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LAN Connect Clock Operations The 82562GZ drives the Platform LAN Connect clock (JCLK) at one of two possible frequencies depending upon its operation speed. When the 82562GZ is in 100BASE-TX mode it drives JCLK at 50 MHz. When the ...
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... Networking Silicon Table 1. 82562GZ Hardware Configuration ISOL ISOL TESTEN _TCK NOTE: Combinations not shown in Table 2. LED Logic Functionality Mode/Configuration Configuration A: 82562ET-compatible Configuration B: Intel GbE mode Configuration C: Alternative mode 6 ISOL_ Mode _TI EXEC 0 1 Reserved 1 0 Reserved Testing 1 1 Power-down Mode Table 1 are reserved and should not be used ...
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... Mode 4: Same as mode 3, except LED configuration C. See table note a. a. Only use this mode if advised Intel representative to compensate for board design issues affecting IEEE compliance. 3.1.1 Pin Usage for Modes and 4 To use modes the following pins need to be reviewed (refer to • ...
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... DUT’s ability to pass regulatory requirements will depend largely on the design of the AFE. The enhanced mode should only be used when 100Base-TX rise/fall times cannot be met in the normal 82562GZ mode. Consult an Intel representative if you are considering using this mode. ...
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Signal Descriptions 4.1 Signal Type Definitions Type Name I Input O Output I/O Input/Output MLT Multi-level analog I/O B Bias DPS Digital Power Supply APS Analog Power Supply 4.2 Twisted Pair Ethernet (TPE) Pins Pin Name Type TDP ...
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Networking Silicon 4.4 Clock Pins Pin Name Type 4.5 Platform LAN Connect Interface Pins Pin Name Type JCLK O JRSTSYNC I JTXD[2:0] I JRXD[2:0] O 4.6 LED Pins Pin Name Type LILED# O ACTLED# ...
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Miscellaneous Control Pins Pin Name Type ADV10/LAN_ I DISABLE# ISOL_TCK I ISOL_TI I ISOL_EXEC I TOUT O TESTEN I 4.8 Power and Ground Connections Pin Name Type VCC DPS VSS DPS Datasheet Description Advertise 10 Mbps Only. The Advertise ...
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Physical Layer Interface Functionality The 82562GZ supports a direct glueless interface to all components that comply with the LAN Connect specification. 5.1 100BASE-TX Mode 5.1.1 100BASE-TX Transmit Blocks The transmit subsection of the 82562GZ accepts 3 bit wide data ...
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Networking Silicon Symbol 5B Symbol Code 5.1.1.2 100BASE-TX Scrambler and MLT-3 Encoder Data is scrambled in 100BASE-TX in order to reduce electromagnetic emissions ...
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Transmit Driver The transmit differential lines are implemented with a digital slope controlled current driver that meets Twisted Pair Physical Media Device (TP-PMD) specifications. Current is sunk from the isolation transformer by the transmit differential pins. The conceptual transmit ...
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Networking Silicon In 100BASE-TX mode, the 82562GZ can detect errors in receive data in a number of ways. Any of the following conditions is considered an error: • Link integrity fails in the middle of frame reception. • ...
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Differential pulses of peak magnitude less than 300 mV. • Continuous sinusoids with a differential amplitude less than 6.2 V MHz. • Sine waves of a single cycle duration starting with 0° or 180° phase that have a differential ...
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Networking Silicon 5.4.1 Auto Plugging Detection The 82562GZ senses the link all the time detects loss of any link activity for more than 6.6 seconds, it indicates to the Media Access Controller (MAC) an “unplugged state” ...
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Platform LAN Connect Registers The following subsections describe PHY registers that are accessible through the LAN Connect management frame protocol. Acronyms mentioned in the registers are defined as follows: SC: Self cleared. RO: Read only. RW: Read/Write. E: EEPROM ...
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Networking Silicon Bit(s) Name 10 Isolate 9 Restart Auto- Negotiation 8 Duplex Mode 7 Collision Test 6:0 Reserved 6.1.2 Register 1: Status Register Bit Definitions Bit(s) Name 15 Reserved 14 100BASE-TX Full-duplex 13 100 Mbps Half- duplex 12 ...
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Bit(s) Name 6 Management Frames Preamble Suppression 5 Auto-Negotiation Complete 4 Remote Fault 3 Auto-Negotiation Ability 2 Link Status 1 Jabber Detect 0 Extended Capability 6.1.3 Register 2: PHY Identifier Register Bit Definitions Bit(s) Name 15:0 PHY ID (high byte) ...
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Networking Silicon 6.1.5 Register 4: Auto-Negotiation Advertisement Register Bit Definitions Bit(s) Name 15 Next Page 14 Reserved 13 Remote Fault 12:5 Technology Ability Field 4:0 Selector Field 6.1.6 Register 5: Auto-Negotiation Link Partner Ability Register Bit Definitions Bit(s) ...
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Bit(s) Name 2 Next Page Able 1 Page Received 0 Link Partner Auto- Negotiation Able 6.2 Medium Dependent Interface Registers 8 through 15 Registers 8 through 15 are reserved for IEEE. 6.3 Medium Dependent Interface Registers 16 through 31 6.3.1 ...
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Networking Silicon Bit(s) Name 6:2 PHY Address 1 Speed 0 Duplex Mode 6.3.2 Register 17: PHY Unit Special Control Bit Definitions Bit(s) Name 15 Scrambler By- pass 14 By-pass 4B/5B 13 Force Transmit H- Pattern 12 Force 34 ...
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Bit(s) Name 2 Extended Squelch 1 Link Integrity Disable 0 Jabber Function Disable 6.3.3 Register 18: Reserved Bit(s) Name 15:0 Reserved 6.3.4 Register 19: 100BASE-TX Receive False Carrier Counter Bit Definitions Bit(s) Name 15:0 Receive False Carrier 6.3.5 Register 20: ...
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Networking Silicon 6.3.7 Register 22: Receive Symbol Error Counter Bit Definitions Bit(s) Name 15:0 Symbol Error Counter 6.3.8 Register 23: 100BASE-TX Receive Premature End of Frame Error Counter Bit Definitions Bit(s) Name 15:0 Premature End of Frame 6.3.9 ...
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Bit(s) Name 4 New mode 3 100BASE-TX Receive Jabber Disable 2:0 LED Switch Control 6.3.12 Register 28: MDI/MDI-X Control Bit Definitions Bit(s) Name 15:8 Reserved 7 Auto Switch Enable 6 Switch 5 Status 4 Auto Switch Complete 3:0 Resolution Timer ...
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Test Port Functionality The 82562GZ’s XOR Tree Test Access Port (TAP) is the access point for test data to and from the device. The port provides the ability to perform basic production level testing. 7.1 Asynchronous Test Mode ...
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Networking Silicon Table 8. XOR Tree Chain Order Chain Order XOR Tree Output TOUT The following pins are not included in the XOR Tree chain: X1, ISOL_TCK, ISOL_EXEC, ISOL_TI and TESTEN. 30 Chain 11 SPDLED# 12 LILED# Datasheet ...
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Voltage and Temperature Specifications 8.1 Absolute Maximum Ratings Maximum ratings are listed below: Case Temperature under Stress . . . . . . . . . . . . . . . . . . . . . . ...
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Networking Silicon 8.2.2 LAN Connect Interface DC Specifications Table 11. LAN Connect Interface DC Specifications Symbol Parameter V Input/Output CCJ Supply Voltage V Input Low Voltage IL V Input High IH Voltage I Input Leakage IL Current V ...
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Table 14. 10BASE-T Receiver Symbol Parameter R Input Differential ID10 Resistance V Input Differential IDA10 Accept Peak Voltage V Input Differential IDR10 Reject Peak Voltage V Input Common ICM10 Mode Voltage NOTES: 1. The input differential resistance is measured across ...
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Networking Silicon 8.3 AC Characteristics Figure 5 defines the conditions for timing measurements. The design must guarantee proper operation for voltage swings and slew rates that exceed the specified test conditions. Figure 5. AC Test Level Conditions 8.3.1 ...
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Auto-Negotiation Fast Link Pulse (FLP) Timing Parameters Table 18. Fast Link Pulse Timing Parameters Symbol T8 T LP_WID FLP_CLK_CLK T10 T FLP_CLK_DATA T11 T FLP_BUR_NUM T12 T FLP_BUR_WID T13 T FLP_BUR_PER Figure 7. Fast Link Pulse ...
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Networking Silicon 8.3.3 100BASE-TX Transmitter AC Specifications Table 19. 100BASE-TX Transmitter Timing Parameters Symbol T14 T JIT 8.3.4 Reset (JRSTSYNC) AC Specifications Table 20. Reset Timing Parameters Symbol T58 T RST_WID T59 T POP_RST Figure 8. Reset Timing ...
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... The 82562GZ is available in leaded and lead-free 196 Ball Grid Array (BGA) package options. The package dimensions are shown in available in the Intel Packaging Handbook, which is available from the Intel Developer website. Figure 9. Dimension Diagram for the 196-pin BGA Note: No changes to existing soldering processes are needed for the 0.32 mm substrate change. ...
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Networking Silicon 9.2 Pinout Information Note: The power (VCC) and ground (VSS) pins have not been finalized and are subject to change. Do not finalize a design with this information. Revised information will be published when the product ...
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Table 21. 82562GZ Pin Assignments Pin Pin Name Number C10 VSS C11 ACTLED# C12 VSS C13 TDP C14 TDN VSS D5 VSS D6 ...
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Networking Silicon Figure 10. 82562GZ Pin Out Diagram VCC VSS VCC VSS ...