ADM6996L-AA-T-1 Lantiq, ADM6996L-AA-T-1 Datasheet - Page 54

• Manufacturer Part Number: ADM6996L-AA-T-1
• Manufacturer: Lantiq

Specifications of ADM6996L-AA-T-1

• Lead Free Status / RoHS Status: Supplier Unconfirmed

Table 25
RESETL
0
Rising edge 01
(30ms)
1 (after 30ms)
Keep at least 30ms after RESETL from 01. ADM6996L/LX will read data from EEPROM. After RESETL if CPU
update EEPROM that ADM6996L/LX will update configuration registers too.
When CPU programming EEPROM & ADM6996L/LX, ADM6996L/LX recognizes the EEPROM WRITE instruction
only. If there is any Protection instruction before or after the EEPROM WRITE instruction, CPU needs to generate
separated CS signal cycle for each Protection & WRITE instruction.
CPU can directly program ADM6996L/LX after 30ms of Reset signal rising edge with or without EEPROM
ADM6996L/LX serial chips will latch hardware-reset value as recommend value. It includes EEPROM interface:
EECS: Internal Pull down 40K resister.
EESK: TP port Auto-MDIX select. Internal pull down 40K resister as non Auto-MDIX mode.
EDI: Dual Color Select. Internal pull down 40K resister as Single Color Mode.
EDO: EEPROM enable. Internal pull up 40K resister as EEPROM enable.
Below Figure is ADM6996L/LX serial chips EEPROM pins operation at different stage. Reset signal is control by
CPU with at least 100ms low. Point1 is Reset rising edge. CPU must prepare proper value on EECS(0), EESK,
EDI, EDO(1) before this rising edge. ADM6996L/LX will read this value into chip at Point2. CPU must keep these
values over point2. Point2 is 200ns after Reset rising edge.
ADM6996L/LX serial chips will read EEPROM content at Point4 which 800ns far away from the rising edge of
Reset. CPU must turn EEPROM pins EECS, EESK, EDI and EDO to High-Z or pull high before Point4.
If user want change state to High-Z or pull high on EEPROM pins, the order is CS-> DI -> DO -> SK is better.
A little bit different with the timing on writing EEPROM. See below graph. Must be carefully is when CS go down
after write a command, SK must issue at least one clock. This is a difference between ADM6996L/LX with
EEPROM write timing. If system without EEPROM then user must write ADM6996L/LX internal register by 93C66
timing. If user uses EEPROM then the writing timing is depend on EEPROM type.
4.6
ADM6996L/LX serial chip’s internal counter or EEPROM access timing
EESK: Similar to the MDC signal.
EDI: Similar to the MDIO signal
ECS: Must keep be kept low.
Data Sheet
RESETL & EEPROM content relationship
Serial Interface Timing
CS
High Impedance
Output
Input
SK
High Impedance
Output
Input
54
Registers DescriptionSerial Interface Timing
DI
High Impedance
Output
Output
Rev. 1.13, 2005-11-22
DO
High Impedance
Input
Input
ADM6996L/LX
Data Sheet