AM79C972BVF\W AMD (ADVANCED MICRO DEVICES), AM79C972BVF\W Datasheet - Page 119
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AM79C972BVF\W
Manufacturer Part Number
AM79C972BVF\W
Description
Manufacturer
AMD (ADVANCED MICRO DEVICES)
Datasheet
1.AM79C972BVFW.pdf
(130 pages)
Specifications of AM79C972BVF\W
Operating Supply Voltage (typ)
3.3V
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Lead Free Status / RoHS Status
Compliant
- Current page: 119 of 130
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1
0
CSR8: Logical Address Filter 0
Bit
31-16
15-0
LADRF[15:0] Logical Address Filter, LADRF-
MIIPDTINTE MII PHY Detect Transition Inter-
MIIPDTINT MII PHY Detect Transition Inter-
Name
RES
Read/Write accessible always.
MCCIINTE
H_RESET and is not affected by
S_RESET or setting the STOP
bit.
Read/Write accessible always.
MIIPDTINT is cleared by the host
by writing a 1. Writing a 0 has no
effect. MIIPDTINT is cleared by
H_RESET and is not affected by
S_RESET or setting the STOP
bit.
Read/Write accessible always.
MIIPDTINTE is set to 0 by
H_RESET and is not affected by
S_RESET or setting the STOP
bit.
Read/Write accessible only when
either the STOP or the SPND bit
management frames. For in-
stance, when MCCIINTE is set to
1 and the Auto-Poll state ma-
chine generates a MII manage-
ment frame, the MCCIINT will set
the INTR bit upon completion of
the MII management frame re-
gardless of the comparison out-
come.
rupt. The MII PHY Detect Transi-
tion Interrupt is set by the
Am79C972 controller whenever
the MIIPD bit (BCR32, bit 14)
transitions from 0 to 1 or vice ver-
sa.
rupt Enable. If MIIPDTINTE is set
to 1, the MIIPDTINT bit will be
able to set the INTR bit.
Description
Reserved locations. Written as
zeros and read as undefined.
[15:0]. The content of this register
is undefined until loaded from the
initialization block after the INIT
bit in CSR0 has been set or a di-
rect register write has been per-
formed on this register.
is
set
to
0
Am79C972
by
CSR9: Logical Address Filter 1
Bit
31-16 RES
15-0 LADRF[31:16] Logical Address Filter, LADRF-
CSR10: Logical Address Filter 2
Bit
31-16 RES
15-0 LADRF[47:32] Logical
CSR11: Logical Address Filter 3
Bit
31-16 RES
15-0 LADRF[63:48] Logical
Name
Name
Name
is set. These bits are unaffected
by H_RESET, S_RESET, or
STOP.
zeros and read as undefined.
[31:16]. The content of this regis-
ter is undefined until loaded from
the initialization block after the
INIT bit in CSR0 has been set or
a direct register write has been
performed on this register.
Read/Write accessible only when
either the STOP or the SPND bit
is set. These bits are unaffected
by H_RESET, S_RESET, or
STOP.
zeros and read as undefined.
LADRF[47:32]. The content of
this register is undefined until
loaded from the initialization
block after the INIT bit in CSR0
has been set or a direct register
write has been performed on this
register.
Read/Write accessible only when
either the STOP or the SPND bit
is set. These bits are unaffected
by H_RESET, S_RESET, or
STOP.
zeros and read as undefined.
LADRF[63:48]. The content of
this register is undefined until
loaded from the initialization
block after the INIT bit in CSR0
has been set or a direct register
Description
Reserved locations. Written as
Description
Reserved locations. Written as
Description
Reserved locations. Written as
Address
Address
Filter,
Filter,
119
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