LAN9420-NU Standard Microsystems (SMSC), LAN9420-NU Datasheet - Page 153

• Manufacturer Part Number: LAN9420-NU
• Manufacturer: Standard Microsystems (SMSC)

Specifications of LAN9420-NU

• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 128
• Lead Free Status / RoHS Status: Compliant

Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface
Datasheet
SMSC LAN9420/LAN9420i
4.6.2
31:24
23:16
14:13
BITS
12:9
7:2
15
8
Data (PM_DATA)
This field is not implemented and returns zeros.
PMCSR PCI to PCI Bridge Support Extensions (PMCSR_BSE)
This field is not implemented and returns zeros.
PME Status (PME_STATUS)
This bit is set when an enabled power management event has been
detected. Writing a “1” to this bit will clear it provided that the source of the
event has been cleared. This bit is level-triggered and will not clear on write
if the source of the power management event remains asserted. Writing a
“0” has no effect.
When the VAUXDET input pin is low, this bit is reset on assertion of a power-
on reset or PCI reset (PCInRST).
When the VAUXDET input pin is high, this bit is unaffected by assertion of
PCI reset (PCInRST). In this case, the bit will maintain its setting until
cleared with a write, or until assertion of a power-on reset.
Data Scale (DATA_SCALE)
This field is not implemented and returns zeros as a result of the PM_DATA
field of this register not being implemented.
Data Select (DATA_SELECT)
This field is not implemented and returns zeros as a result of the PM_DATA
field of this register not being implemented.
PME Enable (PME_EN)
When this bit is set, the device will assert the external nPME signal if the
PME Status (PME_STATUS)
cleared, the device will not assert the external nPME signal.
When the VAUXDET input pin is cleared, this bit is reset on assertion of a
power-on reset or PCI reset (PCInRST).
When the VAUXDET input pin is set, this bit is unaffected by assertion of
PCI reset (PCInRST). In this case, the bit will maintain its setting until
cleared with a write, or until assertion of a power-on reset.
If PME_EN is cleared, the device will automatically place the PHY into
General Power-Down when entering the D3
RESERVED
PCI Power Management Control and Status Register (PCI_PMCSR)
This register controls the device’s power state.
Note: The format of this register is equivalent to offsets 7:4 of the Power Management Register Block
Definition as described in Revision 1.1 of the PCI Bus Power Management Interface
Specification.
Offset:
bit in this register is set. When this bit is
DESCRIPTION
7Ch
DATASHEET
HOT
153
state.
Size:
32 bits
TYPE
R/WC
R/W
RO
RO
RO
RO
RO
Revision 1.4 (12-17-08)
DEFAULT
Note 4.11
Note 4.11
0000b
00h
00h
00b
-