LAN9220-ABZJ Standard Microsystems (SMSC), LAN9220-ABZJ Datasheet - Page 45

• Manufacturer Part Number: LAN9220-ABZJ
• Description: 10/100 NON-PCI ETHERNET CONTROLLER
• Manufacturer: Standard Microsystems (SMSC)

Specifications of LAN9220-ABZJ

• Operating Supply Voltage (typ): 1.8/3.3V
• Operating Supply Voltage (max): 3.6V
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 56
• Lead Free Status / RoHS Status: Compliant

16-bit Non-PCI Small Form Factor 10/100 Ethernet Controller with Variable Voltage I/O & HP Auto-MDIX Support
Datasheet
SMSC LAN9220
MAC and Host
Internal Clock
Management
MAC Power
Interface
BLOCK
Device
PHY
Note 3.16 The PME interrupt status bit on the INT_STS register (PME_INT) is set regardless of the
A write to the BYTE_TEST register, regardless of whether a carrier was detected, will return the
LAN9220 to the D0 state and will reset the PM_MODE field to the D0 state. As noted above, the host
is required to check the READY bit and verify that it is set before attempting any other reads or writes
of the device. Before the LAN9220 is fully awake from this state the EDPWRDOWN bit in register 17
of the PHY must be cleared in order to wake the PHY. Do not attempt to clear the EDPWRDOWN bit
until the READY bit is set. After clearing the EDPWRDOWN bit the LAN9220 is ready to resume
normal operation. At this time the WUPS field can be cleared.
setting of PME_EN.
(NORMAL OPERATION)
Full ON
Full ON
Full ON
Full ON
Table 3.10 Power Management States
D0
KEY
CLOCK ON
BLOCK DISABLED – CLOCK ON
FULL OFF
DATASHEET
RX Power Mgmt. Block
45
Full ON
Full ON
(WOL)
OFF
D1
On
Energy Detect Power-Down
(ENERGY DETECT)
OFF
OFF
OFF
Revision 2.7 (03-15-10)
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