CY7C924ADX-AI Cypress Semiconductor Corp, CY7C924ADX-AI Datasheet - Page 9

• Manufacturer Part Number: CY7C924ADX-AI
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C924ADX-AI

• Number Of Transceivers: 1
• Data Rate: 622Mbps
• Operating Supply Voltage (typ): 5V
• Supply Current (max): 250mA
• Screening Level: Industrial
• Pin Count: 100
• Mounting: Surface Mount
• Package Type: TQFP
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (max): 5.5V
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Not Compliant

Document #: 38-02008 Rev. *E
Pin Descriptions
CY7C924ADX HOTLink Transceiver
21
67
73
77
71
6
12
Number
Control Signals
Pin
RXEMPTY*
RXRST*
RFEN
RXBISTEN*
AM*
LOOPTX
REFCLK
Name
(continued)
3-state TTL output,
changes following
RXCLK↑
TTL input, sampled
on RXCLK↑, Internal
Pull Up
TTL input,
asynchronous,
Internal Pull Up
TTL input,
asynchronous,
Internal Pull Up
TTL input, sampled
by TXCLK↑,
RXCLK↑, and
REFCLK↑
TTL input,
asynchronous,
Internal Pull Down
TTL input clock
I/O Characteristics
Receive FIFO Empty Flag. Active HIGH when configured for Cascade timing
(EXTFIFO is HIGH), active LOW when configured for UTOPIA timing
(EXTFIFO is LOW). The RXFULL* output is enabled when AM* is asserted,
otherwise it is High-Z.
When the Receive FIFO is enabled (FIFOBYP* is HIGH), RXEMPTY* is
asserted when no data remains in the Receive FIFO. Any read operation
occurring when RXEMPTY* is asserted results in no change in the FIFO
status, and the data from the last valid read remains on the RXDATA bus.
When the Receive FIFO is bypassed but the Decoder is enabled, RXEMPTY*
is used as a valid data indicator. The RXMODE[1:0] settings allow the user to
determine which data is valid and allows selective flagging of idle characters.
When RXEMPTY* is deasserted it indicates that a valid character (as selected
by RXMODE[1:0]) is present at the RXDATA outputs. When asserted it
indicates that a C5.0 (K28.5) rejected by the current RXMODE[1:0] setting is
present on the RXDATA output bus.
If both the Receive FIFO and the Decoder are bypassed, RXEMPTY* is
deasserted to indicate that all received characters are valid.
The TXFULL* output is enabled when AM* is asserted, otherwise it is High-Z.
Receive FIFO Reset. When the Receive FIFO is addressed (FIFOBYP* is
HIGH and device is selected by AM*) and RXRST* is sampled asserted for
eight or more RXCLK cycles, a Receive FIFO reset is initiated. The RXRST*
input is also asserted to access the Serial Address Register.
Reframe Enable. Controls when the framer is enabled to adjust the character
boundaries based on detection of one or more K28.5 characters in the data
stream. When HIGH, the framer can adjust the character boundaries relative
to the received serial data stream to match those of the remote transmitter.
When LOW, the boundary is fixed.
Receiver BIST Enable. When asserted, built-in self test (BIST) is active and
the receiver is configured to perform a character for character match of the
incoming data stream with a 511-character BIST sequence. The result of
character mismatches are indicated on RXRVS. Completion of each
511-character BIST loop is accompanied by an assertion pulse on the
RXFULL* flag.
Address Match. This signal is a qualifier for TXEN*, RXEN*, TXRST*, and
RXRST*. It also controls three-state enables for the TXFULL*, TXEMPTY*,
RXFULL*, and RXEMPTY* signals.
Serial-in to Serial-out LOOP Select. This input controls the LOOP-through
function in which the Clock/Data Recovery PLL recovers the serial data and
then retransmits it using the Transmit PLL as the bit rate reference. It selects
between the output of the Transmit FIFO and the output of the Elasticity Buffer
as the input to the Transmit Encoder. When LOW, the Transmit FIFO is the
source of data for transmission. When HIGH, the Elasticity Buffer is the source
of data for transmission and serial input data is reclocked and routed to the
serial outputs.
The LOOPTX function can only be used if the FIFOs are enabled (FIFOBYP*
= HIGH).
Reference Clock. This clock input is the timing reference for the transmit and
receive PLLs. When the Transmit FIFO is bypassed, REFCLK is also the clock
for the external transmit data interface.
See
RANGESEL, FIFOBYP*, ENCBYP* and BYTE8/10*.
Table 5 on page 19
for the relationships among REFCLK, SPDSEL,
Signal Description
CY7C924ADX
Page 9 of 58
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