PEF22554HTV31XP Lantiq, PEF22554HTV31XP Datasheet - Page 9

• Manufacturer Part Number: PEF22554HTV31XP
• Manufacturer: Lantiq

Specifications of PEF22554HTV31XP

• Mounting: Surface Mount
• Package Type: TQFP
• Lead Free Status / RoHS Status: Compliant

8
Page 194/200, Chapter 6.3 and Chapter 7.3, Device Initialization E1 and T1/J1
The following text has been added:
The clock mode must be programmed according to the selected MCLK frequency before
any XL1/2 output is enabled (while the outputs are not yet activated by selection of the
line coding). Otherwise the output pulse width might not match the pulse mask
requirements.
Page 277, Chapter 9.2 and Page 384, Chapter 10.2, Clock Mode Register
programming for E1 and T1/J1
The following text has been added/corrected (for E1 and T1/J1 operation):
Attention: Write operations to GCM5 and/or GCM6 register initiate a PLL reset (see
9
Page 192, Table 46, Initial Values after Reset (E1)
The second row shall read:
2.048
Page 194, Table 47, Initialization Parameters (E1)
The row “Framing additions” shall read:
RC0RC1.ASY4, RC0RC1.SWD
10
Page 221/321, Chapter 9.2/10.2, Register bit CMDR.RMC
Confirmation from CPU to QuadFALC that the current frame or data block has been
fetched following an RPF or RME interrupt, thus the occupied space in the RFIFO can
be released.
is already cleared, the next incoming data block is cleared instantly, although interrupts
are generated.
Addendum
8.192
Clock Mode Selection
below) and must be performed before any port configuration is done.
this is not possible set LIM01.DRS (if not set) of every channel
separately before writing to these registers and reset LIM01.DRS (if it
was not set before) after these write operations.
Device Initialization
HDLC Handling
MHz system clocking rate...
While the FIFO is empty, RMC must not be set.
This might lead to incorrect software behaviour.
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If RMC is given while RFIFO
Clock Mode Selection
QuadFALC
PEF 22554 HT/E
DS1, 2003-07-02
®
V2.1
If