KS8995E Micrel Inc, KS8995E Datasheet - Page 23

• Manufacturer Part Number: KS8995E
• Manufacturer: Micrel Inc

Specifications of KS8995E

• Number Of Primary Switch Ports: 5
• Fiber Support: Yes
• Integrated Led Drivers: Yes
• Phy/transceiver Interface: MII/SNI
• Power Supply Type: Analog/Digital
• Package Type: PQFP
• Data Rate (typ): 10/100Mbps
• Vlan Support: Yes
• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Pin Count: 128
• Mounting: Surface Mount
• Jtag Support: No
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Not Compliant

The table below briefly summarizes priority features. For more detailed settings see the EEPROM register description.
VLAN Operation
The VLAN’s are setup by programming the VLAN Mask Registers in the EEPROM. The perspective of the VLAN is from the
input port and which output ports it sees directly through the switch. For example if port 1 only participated in a VLAN with ports
2 and 5 then one would set bits 1 and 4 in register 8 (Port 1 VLAN Mask Register). Note that different ports can be setup
independently. An example of this would be where a router is connected to port 5 and each of the other ports would work
autonomously. In this configuration ports 1 through 4 would only set the mask for port 5 and port 5 would set the mask for ports
1 through 4. In this way the router could see all ports and each of the other individual ports would only communicate with the
router.
All multicast and broadcast frames adhere to the VLAN configuration. Unicast frame treatment is a function of register 5 bit
6. If this bit is set then unicast frames only see ports within their VLAN. If this bit is cleared unicast frames can traverse VLAN’s.
VLAN tags can be added or removed on a per port basis. Further, there are provisions to specify the tag value to be inserted
on a per port basis.
The table below briefly summarizes VLAN features. For more detailed settings see
August 2003
KS8995E
Register(s)
3
5
3-7
3-7
23-30
3-7
2
3-7
Register(s)
3-7
3-7
5
8-12
13-22
Bit(s)
7-6
7
0
5
7-0
4
7-0
3
Bit(s)
2
1
6
4-0
7-0
Global/Port
Global
Global
Port
Port
Global
Port
Global
Port
Global/Port
Port
Port
Global
Port
Port
Description
General
Priority Control Scheme: Transmit buffer high/low interleave control.
Priority Buffer Reserve: Reserves 12KB of the buffer for high priority traffic.
Enable Port Queue Split: Splits the transmit queue on the desired port for high and low
priority traffic.
DSCP Priority
Enable Port DSCP: Looks at DSCP field in IP header to decide high or low priority.
DSCP Priority Points: Fully decoded 64 bit register used to determine priority from
DSCP field (6 bits) in the IP header.
802.1p Priority
Enable Port 802.1p Priority: Uses the 802.1p priority tag (3 bits) to determine frame
priority.
Priority Classification: Determines which tag values have high priority.
Per Port Priority
Enable Port Priority: Determines which ports have high priority traffic.
Description
Insert VLAN Tags: If specified, will add VLAN tags to frames without existing tags
Strip VLAN Tags: If specified, will remove VLAN tags from frames if they exist
VLAN Enforcement: Allows unicast frames to adhere or ignore the VLAN configuration
VLAN Mask Registers: Allows configuration of individual VLAN grouping. Note reserved
bit in each of the registers (sliding position).
VLAN Tag Insertion Values: Specifies the VLAN tag to be inserted if enabled (see
above)
Table 3. Priority Control
Table 4. VLAN Control
23
“EEPROM Memory Map”
section.
KS8995E
Micrel